IP Generator for Early TAP Estimation in SOC Design
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Solution Overview
Problem
Traditional methods for estimating Timing, Area, and Power (TAP) characteristics in System on a Chip (SOC) designs require detailed physical implementation, leading to inaccurate modeling during the architectural exploration stage and increased time and cost due to the need for revisions and additional simulation testing.
Innovation Solution
An Intellectual Property (IP) Generator that estimates TAP characteristics by creating abstract executable representations for each IP sub-component, allowing for early prediction and reporting of timing, area, and power results through a graphic user interface, enabling users to make design trade-offs before logic synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional physical implementation methods are used for TAP estimation, then detailed physical layout information is obtained, but the design timeline is extended and revisions are required
Solution Approach 1:
The patent performs TAP estimation at the architectural exploration stage, before physical implementation is completed. The system creates executable representations from architectural descriptions and generates TAP estimates preliminarily, allowing design decisions to be made early without waiting for detailed physical layout completion.
Solution Approach 2:
The patent creates executable representations that are simplified copies or abstractions of the actual physical implementation. These executable models capture essential TAP characteristics without requiring the full detailed physical layout, enabling early estimation using representative models rather than complete physical implementations.
2Measurement precision
If detailed physical implementation is performed for accurate TAP modeling, then precise TAP characteristics are obtained, but additional simulation testing and revisions are required
Solution Approach 1:
The system generates TAP estimates during the architectural exploration stage, performing the estimation action preliminarily before detailed implementation. This allows design validation and optimization to occur earlier, reducing the need for later simulation testing and revisions.
Solution Approach 2:
The patent provides dynamic TAP estimation capability that allows designers to evaluate different architectural configurations quickly. The system can re-estimate TAP characteristics when architectural parameters change, enabling iterative design exploration without performing complete detailed simulations for each variation.
3Ease of manufacture
If physical layout is completed before architectural validation, then physical implementation details are established, but design revisions and re-simulation are required
Solution Approach 1:
The patent performs TAP estimation and architectural validation at the exploration stage, before detailed physical implementation is finalized. This preliminary validation identifies potential issues early, preventing costly revisions later in the design process.
Solution Approach 2:
The system introduces an intermediate executable representation layer between architectural description and physical implementation. This intermediary model allows validation and estimation to be performed without committing to detailed physical layout decisions, serving as a buffer that prevents premature optimization.
Data Source
AI summary
Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.