Debug Workspace Reuse for Electronic Design Verification
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Solution Overview
Problem
The process of debugging in electronic design verification is tedious and time-consuming, particularly due to similarities among failed properties that require extensive verification of new waveforms and register-transfer-level (RTL) fixes, leading to repetitive efforts in identifying root causes.
Innovation Solution
A computer-implemented method in an electronic design environment that identifies triggered properties and fan-in signals to determine a start point debug location, generates a debug workspace, and reuses this workspace across different traces, properties, and design revisions, capturing and displaying relative cycles to streamline debugging activities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If users manually verify new waveforms and debug failed properties in electronic design verification, then debugging accuracy can be achieved, but the process becomes tedious and time-consuming
Solution Approach 1:
The system performs preliminary actions by automatically identifying triggered properties and their fan-in signals, determining start point debug locations, and generating debug workspaces before users need to manually debug. This preliminary automation reduces the time users spend on repetitive debugging tasks while maintaining accuracy through systematic analysis of design properties and signals.
Solution Approach 2:
The system creates copies of debug workspaces that can be reused across multiple debugging scenarios. Once a debug workspace is generated for a particular failed property, it can be copied and applied to other similar properties, eliminating the need to manually recreate debugging setups and significantly reducing debugging time while preserving accurate debugging methods.
2Measurement precision
If users apply constraints and create alternate waveforms to debug failed properties, then root cause identification can be achieved, but extensive repetitive debugging efforts are required
Solution Approach 1:
The debug workspace generated by the system serves multiple functions and can be universally applied to different failed properties that share similar structural cone of influence signals. Instead of performing extensive repetitive debugging for each property, the universal debug workspace can be reused across multiple scenarios, maintaining root cause identification accuracy while dramatically improving debugging efficiency.
Solution Approach 2:
The system performs self-service by automatically analyzing design properties, identifying triggered properties, determining fan-in signals, and generating debug workspaces without requiring users to manually apply constraints or create alternate waveforms. This automation maintains accurate root cause identification while eliminating repetitive manual debugging efforts.
3Measurement precision
If users verify RTL fixes by checking new design behavior against problems, then verification accuracy is maintained, but the process becomes tedious
Solution Approach 1:
The system performs self-service verification by automatically comparing new design behavior against the original problems using the generated debug workspace. Instead of requiring users to manually verify RTL fixes, the system autonomously checks whether the fixes resolve the triggered properties, maintaining verification accuracy while significantly improving ease of operation.
Solution Approach 2:
The system implements feedback by using the debug workspace to automatically evaluate whether RTL fixes resolve the identified problems. The verification process provides feedback on the effectiveness of fixes by checking if the triggered properties are resolved, maintaining high verification accuracy while making the process easier to operate through automation.
Data Source
AI summary
The present disclosure relates to a method for reusing a debugging workspace in an electronic design environment. Embodiments may include performing, using a processor, a verification of an electronic design and identifying at least one triggered property associated with the electronic design. Embodiments may further include identifying at least one fan-in signal associated with the at least one triggered property of the electronic design. Embodiments may also include determining a start point debug location based upon, at least in part, the at least one fan-in signal, wherein the start point debug location includes at least one of signal information, cycle information, and event time information. Embodiments may further include generating a debug workspace, wherein generating includes adding at least one additional debug location and storing a cycle of the additional debug location as a relative cycle that is relative to another debug location associated with the debug workspace.