CRC Calculation Decomposition for 3D Memory Layout Efficiency
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Solution Overview
Problem
In 3D memory devices, the large number of through-silicon vias (TSVs) required for transmitting CRC bits and data bits occupy extra area on each die, increasing chip size and power consumption, and the existing methods for error detection using CRC calculations are inefficient in terms of layout space utilization.
Innovation Solution
The solution involves decomposing CRC calculations among CRC calculator circuits of multiple DQ circuits and a DM circuit, with CRC combine circuits receiving CRC calculation bits directly on separate signal lines, reducing the area required for data buses by executing exclusive-OR operations within these circuits, thereby minimizing the need for additional layout space for CRC bit transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC bits are transmitted on additional signal lines of data buses, then error detection capability is improved, but data bus area and chip size increase
Solution Approach 1:
The patent extracts the CRC calculation function from the data bus transmission path and implements it within the memory device using dedicated CRC calculator circuits. This removes the need for separate CRC bit signal lines on the data bus, as the CRC calculation is performed internally using the existing data bits, thereby maintaining error detection capability while reducing data bus area requirements
Solution Approach 2:
The patent makes the existing data bits serve multiple functions: they carry both the actual data information and the CRC check information. By performing CRC calculation within the memory device using the same data bits, the system achieves multi-functionality where the data bus handles both data transmission and error detection without requiring additional dedicated lines
2Object-affected harmful factors
If data buses of bank groups are spaced apart to prevent noise, then noise interference is reduced, but chip area increases
Solution Approach 1:
The patent merges the CRC calculation function with the existing data bus structure by implementing CRC calculators within the memory device. This integration allows the system to maintain noise prevention through proper spacing while reducing the overall chip area, as the combined structure eliminates the need for separate CRC transmission lines that would require additional spacing
3Reliability
If TSVs are used to transmit CRC bits between stacked dies, then error detection is enabled in 3D memory, but chip area and power consumption increase
Solution Approach 1:
The patent extracts the CRC bit transmission function from the TSV interconnect structure by performing CRC calculation entirely within each die using local CRC calculator circuits. This eliminates the need for dedicated TSVs to transmit CRC bits between stacked dies, as each die independently calculates CRC for its data, thereby maintaining error detection capability while reducing TSV area and power consumption
Solution Approach 2:
The patent introduces CRC calculator circuits as intermediary components within each die that perform local CRC calculation. These intermediaries process the data bits locally before transmission, eliminating the need for separate CRC bit transmission paths through TSVs and reducing the burden on the interconnect structure
4Reliability
If TSVs are used to transmit CRC bits between stacked dies, then error detection is enabled in 3D memory, but power consumption increases
Solution Approach 1:
The patent extracts the CRC bit transmission function from the TSV interconnect structure by performing CRC calculation entirely within each die using local CRC calculator circuits. This eliminates the need for dedicated TSVs to transmit CRC bits between stacked dies, as each die independently calculates CRC for its data, thereby maintaining error detection capability while reducing TSV area and power consumption
Data Source
AI summary
Apparatuses and methods of data error check for semiconductor devices are described. An example apparatus includes a plurality of data queue circuits and a CRC combine circuit. The plurality of data queue circuits includes a plurality of CRC calculator circuits. The plurality of CRC calculator circuits includes a CRC calculator circuit. The CRC calculator circuit receives a plurality of data bits and one or more check bits and further provides a plurality of CRC calculation bits. The CRC combine circuit receives the plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further provides a result signal responsive to, at least in part, to the plurality of CRC calculation bits.