Block-Specific Dynamic Voltage Stress Optimization for Wafer Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current DVS tests apply a fixed voltage to all blocks of a die, leading to suboptimal testing and higher defect rates, as they do not account for varying block characteristics and thermal conditions.
Innovation Solution
A dynamic voltage stress (DVS) condition optimization method and system that selects individual blocks, acquires measurement temperatures, generates a correlation table, and adjusts block-specific DVS voltages based on target temperatures to optimize testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed DVS voltage is applied to all blocks of a die, then the testing process is simple and fast, but the testing accuracy and reliability are reduced due to not accounting for varying block characteristics
Solution Approach 1:
The patent applies different DVS voltages to different blocks based on their specific characteristics (e.g., critical layers, weak layout patterns). Each block receives a customized voltage level tailored to its thermal and structural properties, rather than using a uniform voltage across the entire die. This local differentiation improves testing reliability while maintaining efficiency.
Solution Approach 2:
The patent dynamically adjusts the DVS voltage levels based on real-time or pre-determined block characteristics, thermal conditions, and process variations. The voltage assignment is not static but adapts to the specific requirements of each block, enabling optimized testing that responds to varying conditions across the wafer.
2Device complexity
If a fixed DVS voltage is applied to all blocks, then the device complexity is low, but the manufacturing precision and defect detection capability are insufficient
Solution Approach 1:
The patent segments the die into multiple blocks and assigns different DVS voltages to each block based on their specific characteristics. This segmentation allows precise control of testing conditions for each region, improving defect detection precision without requiring complete redesign of the testing system architecture.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on block characteristics, thermal conditions, and process variations. By adjusting voltage levels as a key parameter for each block, the system achieves high manufacturing precision and defect detection capability while maintaining manageable system complexity through parameter optimization rather than structural complexity.
3Ease of manufacture
If standardized DVS testing is used for all blocks, then the process is easy to implement, but the wafer yield is reduced due to not optimizing for block-specific conditions
Solution Approach 1:
The patent implements local quality by tailoring DVS voltage conditions to specific blocks based on their characteristics (critical layers, weak layout patterns). This localized optimization improves wafer yield by ensuring each block receives appropriate testing conditions, while the overall process remains manufacturable through systematic voltage assignment rules.
Data Source
AI summary
A dynamic voltage stress (DVS) condition optimization includes selecting a testing block from a plurality of blocks in a die of a wafer, acquiring a plurality of testing block measurement temperatures of the testing block when the testing block is processed by a DVS testing flow, acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, configuring a tip burnt block temperature based on the testing block measurement temperatures, determining a DVS block target temperature selected from the DVS block predict temperatures based on the correlation table and the tip burnt block temperature, and generating a DVS block voltage for applying to the testing block in the die of the wafer based on the DVS block target temperature.