Block State Confirmation Cell for Flash Memory Read Optimization
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Solution Overview
Problem
Multi-level flash memory devices face increased read time as they store more data bits, requiring more threshold voltage distributions which complicates the process of reading data efficiently.
Innovation Solution
A semiconductor device with block state confirmation cells that store information about the number of data bits written to memory cells, allowing for selective reading and verification of only the necessary data bits, reducing the need to read all bits simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level flash memory stores more data bits in one memory cell, then the storage capacity is improved, but the read time increases
Solution Approach 1:
The patent divides the memory system into memory blocks, each equipped with a block state confirmation cell that tracks the number of written data bits. This segmentation allows the controller to read only the necessary number of data bits from each block based on its state, rather than reading all possible bits, thereby reducing read time while maintaining high storage capacity through multi-level cell operation
2Quantity of substance
If more threshold voltage distributions are used to store more data bits, then the storage capacity is improved, but the complexity of reading data increases
Solution Approach 1:
The patent employs block state confirmation cells that preliminarily store information about the number of data bits written to each memory block. This preliminary action allows the controller to pre-determine how many data bits need to be read from each block, simplifying the reading process and reducing complexity despite using multiple threshold voltage distributions for high-capacity storage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach speeds up the data read operation by allowing the controller to determine and read only the written data bits based on information from the block state confirmation cells, thereby improving the efficiency of data retrieval in multi-level flash memory systems.
Implementation Method 1
A cell transistor of a flash memory may be programmed or erased according to the Fowler-Nordheim (F-N) tunneling mechanism
Implementation Method 2
electrons present in the floating gate may be discharged to the semiconductor bulk according to the F-N tunneling mechanism
Data Source
AI summary
Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.