Read-Only Memories TRIZ Cases

A redundancy scheme reclaims defective non-volatile memory cells by inverting stored data and tracking inversion status.

A control circuit programs memory cell transistors using loop-incrementing voltages to complete data storage.

Bonding a peripheral circuit structure to a vertically stacked cell array reduces manufacturing complexity while improving storage capacity.

A page buffer uses a bit line controller to precharge a sensing node via multiple current paths.

A NAND flash page buffer circuit uses switching mechanisms to manage bit-line voltage levels during sensing operations.

OTP memory segments fuse cells into groups to enable simultaneous programming without increasing high voltage generator capacity.

A storage device engine identifies read temperatures by analyzing value voltage distribution intersections within the subsystem.

Dynamic pass voltage adjustment for unselected cells resolves bit line potential sensing inaccuracies caused by threshold voltage variations.

A daisy chain topology distributes capacitance across memory package chips to maintain signal integrity.

Block state confirmation cells track written bit counts to allow controllers to read only necessary data, reducing read time while maintaining storage capacity.

Interleaved reference cells monitor threshold voltage drift to compensate for degradation, ensuring accurate data retrieval in non-volatile multilevel memory.

Segmented reverse bias operations normalize resistance variations in non-volatile memory arrays, reducing leakage currents and improving read reliability.

A nonvolatile memory controller adjusts read voltage for flag cells to identify the last programmed page during recovery.

Segmented conductive layers function as word lines and drain-side select gate lines to enable simultaneous read operations across multiple pages.

Dual electrode pads supply voltage to anti-fuse memory units via internal and external power sources.

A memory access circuit dynamically adjusts parallel bit width based on available power levels.

Segmented reference voltages resolve the trade-off between data reading reliability and time by enabling faster differential generation.

A memory system adjusts sensing time using tracking logic values to calibrate signal detection.

Applying distinct pre-charge voltages to lower and upper word line zones mitigates upper tail erosion while reducing average current consumption.

A single die circuit merges a floating gate memory with a cross-coupled latch for volatile testing.

Storing erase counts in dedicated dummy cells prevents data loss during power interruptions while enabling even wear distribution across memory blocks.

Position-dependent programming voltages on NAND select transistors prevent punch-through conduction and drain-induced barrier lowering effects.

A semiconductor memory device merges a storage section for setting information with the main memory cell array to share decoders and sense amplifiers.

Flag cell sensing detects charge loss and programmed bit counts in multi-level memory cells, enabling selective re-reading to reduce data retrieval errors.

Control logic manages OTP bits through universal programming modes, resolving the trade-off between secure access and device complexity.

A shared sense amplifier routes signals across multiple memory partitions to enable concurrent read and write operations.

A companion controller chip manages column redundancy for flash memory arrays, reducing on-chip logic complexity and manufacturing costs.

A sensitive amplifier uses a power switch circuit to cut off supply voltage for the clamp circuit during idle periods.

A multi-level memory cell programming method dynamically determines initial bias voltages from recorded threshold states to reduce verification steps.

A semiconductor memory device applies distinct voltage phases to stabilize bit lines and source lines during read operations.

Memory controller verifies data patterns before write operations, preventing corruption caused by inaccurate voltage limit detectors.

Dummy read operations detect threshold voltage degradation to adjust offset levels, reducing read errors during high-density data retrieval.

Controller selectively generates parity bits for nonvolatile memory chips to enhance error correction capacity without increasing chip size.

Differential storage device preserves prior page data during power loss, eliminating hold-up capacitance requirements and verify operations.

Flag and erase prohibition circuits stop redundant erase pulses during simultaneous testing, reducing test time for non-volatile memory arrays.

A compensation circuit applies a control voltage to a sensing transistor gate terminal to stabilize memory readout operations.

Segmenting memory blocks with localized test biases detects retention and disturbance damage without full-block scanning overhead.

A memory controller selects read retry operations or adjusts bit line control times based on read data analysis.

Selection logic analyzes data attributes to choose storage modes, reducing translation overhead time in non-volatile memory systems.

A memory controller retains running information in a register to skip non-volatile reads, reducing power consumption during activation.

Pre-verify operations determine programming shot counts to eliminate intermediate checks, reducing overall memory programming time.

Local write control current generation eliminates wiring resistance effects, ensuring consistent write speed across large memory arrays.

A memory system calculates capacitor capacitance by combining natural discharge voltage changes with constant current extraction data.

Measures threshold voltage distributions to determine optimized voltage levels, eliminating errors caused by program disturb variations.

Replacing ONO capacitors with NMOS capacitors in the same P-well reduces chip size while stabilizing sensing node potential.

Differentiated bitline inhibit voltages suppress program disturb in high-threshold erased cells while reducing current consumption in standard cells.

A semiconductor memory device manages refresh address counting to control wordline activation sequences during testing operations.

A memory controller swaps data between hot and cold blocks to distribute write operations across phase change random access memory cells.