3D Nonvolatile Memory Device Vertical Integration
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in achieving high performance, small size, and low cost, particularly in integrating multiple memory cells in a three-dimensional configuration while ensuring operation reliability.
Innovation Solution
A nonvolatile memory device design featuring a peripheral circuit structure with a cell array structure that includes a common source line layer, buffer insulating layer, contact stop layers, a cell stack with staircase-shaped gate electrodes, and contact structures extending through the cell stack to connect with gate electrodes, enhancing reliability through specific structural and material configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are arranged in a three-dimensional vertical configuration to increase integration density, then the storage capacity and performance are improved, but the manufacturing complexity and reliability challenges increase
Solution Approach 1:
The device is divided into two separate structures (first structure with peripheral circuit and second structure with cell array) that are bonded together. This segmentation allows independent optimization and manufacturing of each structure, reducing overall manufacturing complexity while maintaining high integration density through vertical stacking.
Solution Approach 2:
The patent transitions from two-dimensional planar arrangement to three-dimensional vertical stacking by bonding peripheral circuit and cell array structures vertically. This dimensional change increases storage capacity without proportionally increasing manufacturing complexity, as each layer can be manufactured separately and then bonded.
2Reliability
If multiple contact structures are extended through the cell stack to connect with gate electrodes, then the electrical connectivity and operation reliability are improved, but the manufacturing precision requirements increase
Solution Approach 1:
Contact stop layers are formed in advance within the buffer insulating layer before extending contact structures through the cell stack. This preliminary action provides pre-defined alignment references that simplify subsequent contact formation processes and reduce manufacturing precision requirements while ensuring reliable electrical connectivity.
Solution Approach 2:
The buffer insulating layer with embedded contact stop layers acts as an intermediary structure between the peripheral circuit and cell array. This intermediary provides a controlled interface that facilitates precise contact formation and improves reliability by managing the complexity of direct connections between the two structures.
3Productivity
If the cell array structure is bonded to the peripheral circuit structure in a vertical configuration, then the device integration density is improved, but the bonding process complexity and potential reliability issues increase
Solution Approach 1:
The device is divided into two separately manufacturable structures (first structure with peripheral circuit and second structure with cell array) that are bonded together. This segmentation allows each structure to be optimized and manufactured independently, reducing bonding process complexity while achieving high integration density through vertical stacking.
Solution Approach 2:
The buffer insulating layer and contact stop layers serve as intermediary structures that facilitate the bonding process between the two structures. These intermediaries provide controlled interfaces that simplify bonding operations and reduce potential reliability issues associated with direct bonding of complex structures.
Data Source
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AI summary
A nonvolatile memory device includes a peripheral circuit structure including a peripheral circuit and a first insulating structure covering the peripheral circuit and a cell array structure bonded to the peripheral circuit structure and including a cell region and a connection region, wherein the cell array structure includes a common source line layer, a buffer insulating layer on the common source line layer, a plurality of contact stop layers buried in the buffer insulating layer, a cell stack which includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked on the buffer insulating layer, a plurality of cell channel structures extending to the common source line layer by passing through the cell stack, a plurality of contact structures each connected to one or more of the plurality of gate electrodes, and a second insulating structure covering the cell stack.