Reverse Bias Trim for Non-Volatile Memory Resistance Uniformity
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Solution Overview
Problem
Non-volatile memory arrays with passive element memory cells face challenges in reliable fabrication, programming, and reading due to high leakage currents, program disturbances, and resistance variations among cells, limiting bandwidth and accuracy in read and write operations.
Innovation Solution
A reverse bias trim operation is applied to non-volatile memory cells to adjust their resistance levels, where a first reverse bias sets the cells to a target resistance state, and a second, smaller reverse bias adjusts cells that are deeply reset back to this state, ensuring all cells reach the desired resistance level without affecting those already correctly set.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a first reverse bias is applied to reset memory cells to a target resistance state, then the cells are set to the desired resistance level, but some cells become deeply reset to a resistance level beyond the target, causing resistance variation and reduced reliability
Solution Approach 1:
The reset operation is segmented into two distinct phases: a first reverse bias applied to all selected cells to achieve initial reset, and a second, smaller reverse bias applied only to cells that became deeply reset. This segmentation allows different cells to receive different treatment based on their state, correcting resistance variations without affecting cells already at the target level.
Solution Approach 2:
The control circuitry incorporates feedback by first applying the initial reverse bias and then detecting which cells require additional trimming. Based on this feedback about cell states, a second reverse bias is selectively applied only to cells that are deeply reset, thereby correcting resistance variations while maintaining cells at the target level unchanged.
2Reliability
If a strong reverse bias is applied to ensure complete reset of all cells, then all cells reach the reset state, but leakage currents increase and read disturbances occur
Solution Approach 1:
The reverse bias is applied dynamically in two stages with different magnitudes. The first stage uses a stronger bias to ensure complete reset of all cells, while the second stage uses a smaller, more controlled bias to trim only deeply reset cells. This dynamic adjustment reduces overall leakage currents and read disturbances compared to applying a constantly strong bias.
Solution Approach 2:
The patent applies partial action by selectively applying the second reverse bias only to the subset of cells that are deeply reset, rather than applying the same strong bias to all cells. This partial application corrects excessive reset in problematic cells while avoiding unnecessary strong bias in cells already at the target level, thereby reducing harmful leakage currents.
3Manufacturing precision
If individual cell resistance variations are corrected through trimming operations, then resistance uniformity improves, but the complexity of the control system increases
Solution Approach 1:
The control circuitry merges the reset and trim operations into a unified process. The same control circuitry that manages the initial reverse bias also manages the second trimming bias, and both operations are coordinated through a single control sequence. This merging approach corrects resistance variations while avoiding the need for separate, complex control systems for each operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces leakage currents, improves the reliability of read and write operations by normalizing resistance levels across memory cells, allowing for higher bandwidth and more accurate data storage.
Implementation Method 1
resistance change element undergo a reverse bias reset operation to change its resistance from a set state at a first level of resistance to a reset state at a second level of resistance
Data Source
AI summary
A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.