Selective Bitline Inhibit Voltage for Program Disturb
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Solution Overview
Problem
Non-volatile semiconductor memory devices face program disturb issues due to higher threshold voltage in erased cells during programming operations, leading to inefficiencies and increased cell current consumption.
Innovation Solution
Implementing a method to detect erased cells with higher program disturb and applying a higher bitline inhibit voltage only to those cells during specific program pulses, while maintaining lower voltages for cells within acceptable threshold voltages, thereby reducing cell current consumption and improving programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a higher bitline inhibit voltage is applied to all cells during programming, then program disturb performance is improved, but cell current consumption increases
Solution Approach 1:
The patent applies different bitline inhibit voltages to different groups of memory cells based on their specific needs. Cells with higher threshold voltages (which experience more program disturb) receive a first bitline inhibit voltage, while cells with lower threshold voltages receive a second bitline inhibit voltage. This localized differentiation resolves the contradiction by providing enhanced protection only where needed, rather than uniformly across all cells.
Solution Approach 2:
The patent dynamically adjusts the bitline inhibit voltage parameter based on the threshold voltage characteristics of memory cells. By detecting the threshold voltage distribution and adapting the inhibit voltage levels accordingly, the system optimizes program disturb suppression while minimizing unnecessary current consumption in cells that don't require high inhibit voltages.
2Reliability
If a higher bitline inhibit voltage is applied to all cells during programming, then program disturb is suppressed, but programming efficiency decreases due to increased power penalty
Solution Approach 1:
The patent implements localized quality control by applying higher bitline inhibit voltages only to specific cell groups that exhibit program disturb issues, while using lower voltages for other cells. This selective approach maintains reliable program disturb suppression where necessary while preserving programming efficiency overall by reducing the power penalty on cells that don't require high inhibit voltages.
Solution Approach 2:
The patent applies excessive action (higher inhibit voltage) only partially to the subset of cells that need it, rather than applying it to all cells. This partial application of excessive action achieves sufficient program disturb suppression for problematic cells while avoiding the efficiency loss that would result from applying high voltages universally.
3Device complexity
If uniform bitline inhibit voltage is applied to all cells, then device complexity is reduced, but program disturb performance deteriorates for cells with higher threshold voltage
Solution Approach 1:
The patent transitions from uniform voltage application to localized quality-based voltage differentiation. By grouping cells according to their threshold voltage characteristics and applying appropriate inhibit voltages to each group, the system achieves improved program disturb performance for cells with higher threshold voltages while maintaining manageable device complexity through systematic classification and control.
Solution Approach 2:
The patent performs preliminary classification of memory cells based on their threshold voltage characteristics before applying programming operations. This preliminary action enables the system to pre-determine which cells will receive higher inhibit voltages and which will receive lower voltages, allowing for optimized program disturb suppression without excessive complexity during the actual programming process.
Data Source
AI summary
A non-volatile semiconductor memory device includes non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.