OTP Memory Control via Multiplexing and Logic

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Solution Overview

Problem

One-time programmable memory with laser fuses consumes a large area on integrated circuits and is programmed before leaving the manufacturer, necessitating an improved system and method for control.

Innovation Solution

A system and method for controlling one-time-programmable memory that includes a hardware bus with multiple capabilities, an OTP memory bank for storing bits that can be written only once, and logic to determine and set these bits based on functionality, allowing for pin-level access and restricted access to memory locations, with features like multiplexing and shadow registers for secure and efficient operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If laser fuses are used for one time programmable memory, then programming capability is achieved, but area consumption increases

Engineering Contradiction:
Improveprogramming capabilityVSAvoidarea consumption
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the programming capability from the physical fuse structure and implements it through logical control mechanisms. Instead of using laser fuses that physically break connections, the invention uses OTP memory banks with control logic that achieves one-time programming through software-controlled bit setting, thereby eliminating the need for large-area fuse structures while maintaining programming functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If OTP memory is programmed before leaving the manufacturer, then secure programming is achieved, but flexibility is reduced

Engineering Contradiction:
Improvesecure programmingVSAvoidflexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamic control mechanisms that allow the OTP memory to be programmed at different stages. The system includes control logic that can determine whether to program the OTP memory bank based on operational conditions, enabling both pre-manufacturing programming for security and post-manufacturing programming for flexibility, thus making the programming timing adaptable rather than fixed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention creates a universal programming system that can operate in multiple modes: pre-manufacturing programming for security applications and post-manufacturing programming for flexible applications. The control logic universally handles both scenarios through the same hardware structure, allowing the system to serve both secure and flexible requirements without requiring separate programming mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If pin-level access is implemented for OTP memory, then access control is improved, but device complexity increases

Engineering Contradiction:
Improveaccess controlVSAvoiddevice complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges the pin-level access control functionality with the existing OTP memory structure by integrating control logic that operates within the memory bank itself. Instead of adding separate complex access control circuits, the invention combines access control with the memory addressing and data path, allowing pin-level access control to be achieved through unified logic that reduces overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8189384B2System and method to control one time programmable memory
Publication Date: 2012.05.29 NORTH STAR INNOVATIONS
  • US8189384B2 patent drawing
  • US8189384B2 patent drawing
  • US8189384B2 patent drawing

AI summary

A device includes a one-time-programmable memory including multiple random accessible input/output pins. Each random accessible I/O pin corresponds to a unique memory address in the one-time-programmable memory. The device also includes a multiplexing circuit with multiple inputs. Each of the multiple inputs is coupled to one of the multiple random accessible I/O pins. An output of the multiplexing circuit has a bit width that is less than the number of the multiple random accessible I/O pins.