Semiconductor Memory Refresh Address Control for Power Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices face increased error possibilities due to high integration and large memory capacity, leading to inefficient refresh operations during testing, which result in increased power consumption and noise, potentially causing data loss despite the absence of defects.
Innovation Solution
A semiconductor memory device with a refresh address counting block that outputs a 14-bit refresh address for both normal and preliminary wordlines, allowing sequential activation and resetting during testing to prevent simultaneous refresh operations and reduce power noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simultaneous refresh operations are performed on both normal block and redundancy block, then refresh coverage is improved, but power consumption and noise increase
Solution Approach 1:
The patent implements dynamic control of refresh operations by detecting test mode signals and automatically adjusting refresh behavior. During test mode, only the normal block undergoes refresh operations while the redundancy block is excluded, whereas during normal operation both blocks are refreshed. This dynamic adaptation resolves the contradiction by optimizing power consumption based on operational context while maintaining adequate refresh coverage.
Solution Approach 2:
The patent changes the refresh operation parameters based on the operational mode. By monitoring the test mode signal state, the system modifies which blocks undergo refresh operations - switching between refreshing only the normal block (test mode) and refreshing both normal and redundancy blocks (normal mode). This parameter change approach allows the system to maintain reliability while controlling power consumption according to actual needs.
2Reliability
If simultaneous refresh operations are performed on both normal block and redundancy block, then refresh coverage is improved, but noise increases causing data loss
Solution Approach 1:
The system dynamically adjusts refresh operations based on operational mode detection. During test mode, refresh operations are restricted to the normal block only, preventing noise generation from simultaneous redundancy block refresh. During normal operation, both blocks are refreshed to ensure adequate coverage. This dynamic control resolves the contradiction by adapting noise generation to actual operational requirements.
Solution Approach 2:
The patent implements parameter changes in refresh operations by conditionally enabling or disabling refresh based on test mode signal detection. When in test mode, the refresh parameter is set to affect only the normal block; when in normal mode, the parameter allows both blocks to be refreshed. This conditional parameter adjustment prevents harmful noise while maintaining necessary refresh coverage.
3Reliability
If refresh address counter counts for both normal and preliminary wordlines, then address coverage is improved, but control complexity increases
Solution Approach 1:
The patent extracts the control logic for differential refresh behavior from the main refresh control flow by implementing a dedicated test mode detection mechanism. This separate extraction allows the system to automatically distinguish between test and normal modes, simplifying the overall control structure while maintaining comprehensive address coverage through mode-appropriate refresh operations.
Solution Approach 2:
The refresh address counter is designed with multi-functionality to serve both normal and redundancy blocks under different operational conditions. By implementing a universal counter that adapts its behavior based on test mode detection, the system achieves comprehensive address coverage without requiring separate counters for each block, thereby reducing control complexity while maintaining reliability.
Data Source
AI summary
A semiconductor memory device for consuming a uniform amount of current includes a memory cell block including a N normal wordline and a M preliminary wordline; a refresh address counting block for outputting a refresh address, having a plurality of bits, corresponding to the N normal wordline and the M preliminary wordline; a refresh counting control block for resetting the refresh address counting block when the refresh address counts a predetermined count during a test mode; and a row decoding block for refreshing unit cells coupled to the N normal wordline and unit cells coupled to the M preliminary wordline of the memory cell block according to the refresh address and a redundancy control signal outputted from the refresh counting control block, wherein M, N are positive integers.