NAND String Select Transistor Gate Voltage Control for Program Disturb
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Solution Overview
Problem
Non-volatile storage systems, particularly in NAND architecture, face challenges with program disturb due to leakage issues such as punch-through conduction, drain-induced barrier lowering (DIBL), and gate-induced drain leakage (GIDL), which affect the reliability and accuracy of data storage as memory arrays scale down.
Innovation Solution
The method involves applying programming conditions that depend on the location of the selected word line, including varying the width or duration of programming pulses, voltages applied to common source lines, bit lines, and select transistors, to prevent or reduce leakage and maintain the boosted channel voltage, thereby reducing program disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory arrays are scaled down to increase storage density, then storage capacity is improved, but leakage current increases causing program disturb
Solution Approach 1:
The patent applies different voltage levels to different word lines based on their position in the NAND string. Word lines closer to the select transistors receive different voltages than those farther away, creating localized voltage conditions that prevent punch-through conduction and DIBL effects in specific regions where they are most problematic.
Solution Approach 2:
The patent dynamically changes voltage parameters (magnitude and duration) of programming pulses based on word line location. By adjusting these parameters, the patent optimizes programming effectiveness while minimizing leakage current and program disturb in scaled-down memory structures.
2Reliability
If programming voltage pulses are applied to program memory cells, then data storage is achieved, but leakage current causes program disturb in adjacent cells
Solution Approach 1:
The patent creates localized voltage conditions by applying position-dependent voltages to different word lines. This ensures that programming voltage is effectively applied to the selected cell while adjacent cells experience voltage conditions that prevent unintended programming or data disturbance.
Solution Approach 2:
The patent applies preliminary voltage conditions to word lines before programming occurs. By pre-establishing appropriate voltage levels on unselected word lines, the patent prevents punch-through conduction and DIBL effects that would otherwise cause program disturb in adjacent memory cells.
3Length of moving object
If select transistor channel length is reduced to increase density, then storage density is improved, but punch-through conduction and DIBL effects increase
Solution Approach 1:
The patent compensates for the reduced channel length by dynamically adjusting voltage parameters. By applying higher or differently timed voltages to word lines based on their position, the patent maintains effective control over the shortened channel, preventing punch-through conduction and DIBL effects that become more prominent with shorter channels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes program disturb by optimizing voltage and pulse conditions based on word line location, enhancing the reliability and accuracy of data storage in non-volatile storage systems.
Implementation Method 1
One of the select transistors (source side select transistor) connects/disconnects the NAND string to a source line
Implementation Method 2
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region
Implementation Method 3
The threshold voltage (V TH ) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.