NMOS Capacitor Sensing Node for Flash Memory Chip Size Reduction
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Solution Overview
Problem
The existing page buffer/sense circuits in flash memory devices require larger chip sizes due to the use of ONO capacitors for sensing nodes, which are formed in a different P-well than the NMOS transistors, leading to increased proprietary area and integration challenges as memory cell arrays become more integrated.
Innovation Solution
Replacing ONO capacitors with NMOS capacitors, which are formed in the same P-well as the NMOS transistors, and implementing a selective charging circuit with a floating node for the sensing node, allowing pre-charging before data transfer to stabilize the potential and prevent wrong verification results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ONO capacitors are used for sensing nodes, then sensing capability is improved, but chip size increases
Solution Approach 1:
The patent merges the sensing node capacitor formation with the NMOS transistor fabrication process by forming the capacitor in the same P-well as the NMOS transistors. This integration eliminates the need for separate ONO capacitor structures and allows shared process steps, thereby reducing overall chip area while maintaining sensing functionality.
Solution Approach 2:
The P-well structure is designed to serve dual purposes: as the substrate for NMOS transistors and as the formation region for sensing node capacitors. This multi-functional use of the P-well eliminates dedicated capacitor areas and reduces the total chip footprint while preserving the large capacitance needed for sensing.
2Measurement precision
If ONO capacitors are used for sensing nodes, then data compensation is improved, but device complexity increases
Solution Approach 1:
The patent combines the capacitor formation process with the NMOS transistor fabrication by using the same P-well for both structures. This merging eliminates separate processing steps for ONO capacitor creation and reduces structural diversity, thereby simplifying the overall device architecture while maintaining data compensation capabilities.
Solution Approach 2:
The patent achieves homogeneity by using uniform process conditions and materials for both NMOS transistor and capacitor formation within the P-well. This homogeneous approach eliminates the need for specialized ONO capacitor processing and simplifies manufacturing while preserving the electrical characteristics needed for data compensation.
3Measurement precision
If selective charging is performed on sensing node, then verification accuracy is improved, but operation complexity increases
Solution Approach 1:
The patent implements preliminary charging of the floating node before the actual sensing operation. This pre-charging action prepares the sensing node in advance, ensuring accurate verification by establishing the correct initial potential state, while the automation of this sequence through circuit design minimizes the complexity burden on external control.
Solution Approach 2:
The patent introduces a floating node as an intermediary element that mediates between the control logic and the sensing node. This intermediary simplifies the control interface by absorbing complex charging sequences internally, allowing external control to remain simple while achieving precise verification through the floating node's automated charge transfer mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the chip size of semiconductor storage devices and stabilizes the potential of the sensing node, preventing incorrect verification during operations, thus enhancing the efficiency and accuracy of data readout and programming.
Implementation Method 1
The sensing node SNS includes an N-type metal oxide semiconductor (NMOS) capacitor
Implementation Method 2
a transistor BLCD used for transferring charges between the sensing node SNS and a latch node SLR
Implementation Method 3
a transistor BLPRE used for pre-charging the bit line with a voltage provided by a voltage supply portion V1
Implementation Method 4
a transistor BLCLAMP used for clamping the bit line
Data Source
AI summary
A semiconductor storage device with a smaller chip size than prior art and a readout method are provided. The semiconductor storage device includes a memory cell array; a page buffer/sense circuit having a sensing node for sensing readout data from a selected page of the memory cell array and a latch circuit for holding data sensed by the sensing node; and a controller controls operations on the memory cell array. The sensing node includes an NMOS capacitor.