Single Die OTP Memory With Clearable Latch

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Solution Overview

Problem

Existing one-time programmable (OTP) circuits are either volatile or non-volatile, but not both, which limits their application in testing and storage, and they cannot be easily changed once programmed, leading to inefficiencies in determining and storing correct values.

Innovation Solution

A single OTP circuit that combines a non-volatile memory with a clearable latch, allowing for both volatile testing and non-volatile storage, enabling the circuit to be programmed with a test value and then burn it into a non-volatile memory, reducing physical footprint and improving testing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate volatile and non-volatile memory circuits are used, then testing and storage functions are available, but device size and complexity increase

Engineering Contradiction:
Improvetesting and storage capabilityVSAvoidcircuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines a volatile latch circuit and a non-volatile OTP memory circuit into a single integrated circuit device. The latch circuit (comprising first and second cross-coupled inverters) is merged with the OTP memory cell (including floating gate transistor and storage node) on the same die, allowing both volatile testing and non-volatile storage functions to coexist in one device, thereby reducing overall device size and simplifying the system architecture.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The integrated circuit is designed to perform multiple functions: the latch circuit provides volatile storage for testing purposes, while the OTP memory provides non-volatile storage for permanent data retention. The same physical device can thus serve both as a testable volatile memory and as a programmed non-volatile memory, eliminating the need for separate dedicated circuits for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If OTP circuit is programmed immediately without testing, then programming speed is improved, but reliability decreases due to potential incorrect values

Engineering Contradiction:
Improveprogramming speedVSAvoiddata accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The latch circuit is configured to receive and hold test values before the OTP memory is programmed. This preliminary storage in the volatile latch allows the circuit to be tested and verified for correctness before committing the data to the non-volatile OTP memory through the burn process. The latch acts as a buffer that enables pre-verification of data integrity prior to permanent programming.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If correct values are determined through testing, then data accuracy is improved, but time and complexity increase

Engineering Contradiction:
Improvedata accuracyVSAvoidtesting duration
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

By integrating the latch and OTP memory in a single circuit, the testing process can be performed in-place without requiring external test equipment or separate test circuits. The latch is directly accessible and can be programmed with test values that are immediately evaluated, reducing the time and complexity associated with external testing procedures while maintaining data accuracy.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10297334B2Single circuit one-time programmable memory and volatile memory
Publication Date: 2019.05.21 TEXAS INSTRUMENTS INC
  • US10297334B2 patent drawing
  • US10297334B2 patent drawing
  • US10297334B2 patent drawing

AI summary

A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.