Storage Device Selective Parity Bit Allocation
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Solution Overview
Problem
Existing storage devices face challenges in efficiently managing parity bits for error correction, particularly as memory cell endurance degrades, leading to increased chip size and reduced error correction capacity when parity bits are stored alongside data.
Innovation Solution
A storage device comprising a first nonvolatile memory chip, a second nonvolatile memory chip, and a controller that selectively generates and allocates parity bits based on the endurance of memory cells, storing additional parity bits in the second chip to enhance error correction capacity without increasing the first chip's size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits are stored in the same memory chip as data, then error correction capacity is provided, but chip size increases and error correction capacity is reduced when memory cell endurance degrades
Solution Approach 1:
The patent divides the storage system into two separate nonvolatile memory chips: a first chip for storing data and a second chip for storing parity bits. This segmentation allows the data chip to maintain its original size while the parity bits are stored in a dedicated separate location, resolving the contradiction between providing error correction capacity and maintaining chip size.
Solution Approach 2:
The controller acts as an intermediary that manages the selective generation and allocation of parity bits. It monitors memory cell endurance and dynamically decides whether to generate additional parity bits in the second chip, mediating between the data storage function and error correction enhancement without requiring permanent expansion of the first chip.
2Reliability
If additional parity bits are generated to maintain error correction capacity as memory cell endurance degrades, then error correction capacity is maintained, but chip size increases
Solution Approach 1:
The system implements dynamic parity bit management where the controller monitors memory cell endurance (PE cycles) and selectively generates additional parity bits in the second chip only when needed. This dynamic approach allows error correction capacity to be maintained as endurance degrades without permanently increasing the first chip's size, as parity bits are added selectively in a separate chip.
Solution Approach 2:
The patent transitions from a single-dimension solution (adding parity bits within the same chip) to a multi-dimensional solution by utilizing a second separate nonvolatile memory chip. This dimensional change allows the system to expand error correction capacity without increasing the physical size of the original data storage chip.
3Reliability
If parity bits are stored in the first nonvolatile memory chip, then error correction is provided, but the chip's endurance is reduced due to additional write cycles
Solution Approach 1:
By segmenting the storage function into two separate chips - first chip for data and second chip for parity bits - the patent eliminates the conflict where parity bit updates would consume the endurance of the data chip. Each chip now experiences only its necessary write cycles, preserving the overall system endurance while maintaining error correction capability.
Data Source
AI summary
A storage device includes a first nonvolatile memory chip; a second nonvolatile memory chip; and a controller. The controller may include a processor configured to execute a flash translation layer (FTL) loaded onto an on-chip memory; an ECC engine configured to generate first parity bits for data and to selectively generate second parity bits for the data, under control of the processor; and a nonvolatile memory interface circuit configured to transmit the data and the first parity bits to the first nonvolatile memory chip, and to selectively transmit the second parity bits selectively generated to the second nonvolatile memory chip.