NAND Flash Memory Read Sensing Voltage Control

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Solution Overview

Problem

NAND-type flash memory experiences reliability issues with data read due to variations in read currents caused by the sequential writing process, where memory cells closer to the bit line have higher threshold voltages, leading to inaccurate sensing of bit line potential changes.

Innovation Solution

A non-volatile semiconductor storage device design that applies a higher voltage to the gates of unselected memory cells during read operations, with the selected memory cell closer to the bit line, to ensure accurate sensing of bit line potential changes, thereby addressing the reliability issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sequential writing is performed from the memory cell closest to the source line, then data can be written to memory cells sequentially, but memory cells closer to the bit line have higher threshold voltages causing inaccurate sensing

Engineering Contradiction:
Improvesequential writing efficiencyVSAvoidbit line potential sensing accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent inverts the conventional sequential writing direction by writing from the memory cell closest to the bit line toward the source line. This reversal ensures that memory cells closer to the bit line are written first with lower threshold voltages, while cells closer to the source line are written later with higher threshold voltages, thereby eliminating the sensing inaccuracy problem while maintaining sequential writing efficiency

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent applies different threshold voltage conditions to different regions of the memory cell array based on their position. By controlling the writing process to apply lower threshold voltages to cells near the bit line and higher threshold voltages to cells near the source line, the system achieves uniform sensing characteristics across all memory cells while maintaining the benefits of sequential writing

Inventive Principle:
Principle #3Local quality

2Measurement precision

If higher voltage is applied to gates of unselected memory cells during read operation, then read accuracy is improved, but device complexity increases

Engineering Contradiction:
Improveread operation accuracyVSAvoidvoltage control complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent dynamically adjusts the read pass voltage based on the position of the selected memory cell within the string. When a cell closer to the bit line is selected, a higher read pass voltage is applied to ensure accurate sensing. When a cell closer to the source line is selected, a lower read pass voltage is used. This dynamic voltage adjustment improves read accuracy without requiring complex additional circuitry, as the voltage control is implemented through software or control logic

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances the accuracy of data read operations by maintaining consistent read currents across memory cells, regardless of their position, thereby improving the reliability of data retrieval in NAND-type flash memory.

Implementation Method 1

the control circuit is configured to, at the time of the read operation, apply a higher voltage to gates of unselected memory cells as a selected memory cell is located at a region closer to the first wiring

Methodology Applied
Scientific EffectElectric Field: Electric Field

Data Source

PatentUS8194465B2Non-volatile semiconductor storage device
Publication Date: 2012.06.05 KIOXIA CORP
  • US8194465B2 patent drawing
  • US8194465B2 patent drawing
  • US8194465B2 patent drawing

AI summary

A non-volatile semiconductor storage device according to one aspect has a memory cell array, a first wiring, a second wiring, and a control circuit. The control circuit is configured to, at the time of the write operation, control the write operation in each of the memory strings such that a memory cell positioned closer to the second wiring is subject to the write operation earlier, and the write operation sequentially proceeds to farther memory cells. On the other hand, the control circuit is also configured to, at the time of the read operation, apply a higher voltage to gates of unselected memory cells as a selected memory cell is located at a region closer to the first wiring.