Memory Cell Transistor Programming with Loop-Adjusted Voltage

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Solution Overview

Problem

Memory devices face challenges in efficiently programming and verifying multiple cell transistors, especially when some transistors are degraded, leading to wider threshold voltage distributions and reduced read margins due to increased programming ease and potential verification errors.

Innovation Solution

A memory device with a control circuit that performs programming in multiple loops, incrementing the program voltage and adjusting verification voltages based on the number of loops required to complete programming, ensuring accurate data storage across multiple levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If programming voltage is increased to program degraded transistors, then programming completeness is improved, but read margin decreases due to wider threshold voltage distribution

Engineering Contradiction:
Improveprogramming completenessVSAvoidread margin
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent segments the programming process into multiple loops (first loop and second loop) with different programming voltages. The first loop uses a lower programming voltage to program non-degraded transistors, while the second loop uses a higher programming voltage to program degraded transistors. This segmentation allows the system to handle different transistor conditions separately, ensuring complete programming while maintaining read margin for non-degraded transistors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts the programming voltage based on the loop number and verification results. The control circuit applies different programming voltages in different loops, and the verification voltage is also adjusted dynamically. This dynamic approach allows the system to adapt to the actual state of transistors during programming, ensuring that degraded transistors receive sufficient voltage while non-degraded transistors are not over-programmed.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If verification voltage is increased to verify degraded transistors, then verification accuracy for degraded transistors is improved, but verification errors increase for non-degraded transistors

Engineering Contradiction:
Improveverification accuracy for degraded transistorsVSAvoidverification accuracy for non-degraded transistors
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent segments the verification process into different stages corresponding to different loops. The first verification uses a first verification voltage appropriate for non-degraded transistors, while the second verification uses a second verification voltage appropriate for degraded transistors. This segmentation ensures that each verification stage uses the appropriate voltage level, preventing verification errors in non-degraded transistors while maintaining accuracy for degraded transistors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control circuit dynamically adjusts the verification voltage based on the current loop and the state of transistors. The verification voltage is increased in the second loop to accurately verify degraded transistors, while in the first loop, a lower verification voltage is used to avoid verification errors in non-degraded transistors. This dynamic adjustment ensures verification accuracy across different transistor conditions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10410725B2Memory device and a method for programming memory cell transistors
Publication Date: 2019.09.10 KIOXIA CORP
  • US10410725B2 patent drawing
  • US10410725B2 patent drawing
  • US10410725B2 patent drawing

AI summary

A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.