Semiconductor Memory Device Merging Storage Section With Main Array
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Solution Overview
Problem
As semiconductor memory devices like NOR type flash memory increase in capacity, the number of decoders and sense amplifiers needed to store setting information also increases, leading to a rise in chip area requirements.
Innovation Solution
The implementation of multiple memory cell arrays with decoders and switch circuits that allow for efficient selection and reading of memory cells, along with a latch circuit and control circuit to manage setting information, reduces the need for additional decoders and sense amplifiers, thereby minimizing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity of the storage section is increased to store more setting information, then the number of decoders and sense amplifiers increases, but the chip area increases
Solution Approach 1:
The patent merges the storage section for setting information with the main memory cell array, allowing both to share the same decoders and sense amplifiers. This integration enables the system to store both user data and setting information without requiring separate decoding and sensing resources, thereby increasing memory capacity without proportionally increasing chip area.
Solution Approach 2:
The decoders and sense amplifiers are designed to serve multiple functions: they can read both user data from the main memory array and setting information from the storage section. This multi-functionality allows a single set of decoding and sensing resources to handle multiple memory regions, reducing the total number of components needed and minimizing chip area while supporting increased memory capacity.
2Quantity of substance
If memory capacity is enlarged, then the amount of setting information increases, but the number of decoders and sense amplifiers must increase
Solution Approach 1:
The storage section for setting information is merged with the main memory cell array, allowing both memory regions to share the same decoders and sense amplifiers. This eliminates the need for separate decoding and sensing resources for each memory region, thereby reducing device complexity while supporting increased amounts of setting information.
Solution Approach 2:
The decoders and sense amplifiers are designed with universal functionality to read from both the main memory array and the storage section. This multi-functionality allows a single set of components to handle multiple memory regions, reducing the total number of decoders and sense amplifiers needed while supporting enlarged memory capacity and increased setting information storage.
Data Source
AI summary
A device includes first and second memory cell arrays, first and second decoders, first and second sense amplifiers, and first and second switch circuits. The first switch circuit switches the supply of writing and erasing voltages or a reading voltage to the first memory cell array, and switches the supply of writing and erasing addresses or a reading address to the first decoder, and switches the connection of a data line connected to the first memory cell array to the first sense amplifier. The second switch circuit switches the supply of writing and easing voltages or a reading voltage to one of the second memory cell arrays, and switches the supply of writing and erasing addresses or a reading address to one of the second decoders, and switches the connection of a data line connected to the second memory cell arrays to the second sense amplifier.