Non-volatile Memory Erase Prohibition Circuit
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Solution Overview
Problem
Simultaneous erase testing of non-volatile semiconductor memory devices often results in unnecessary erase operations due to varying manufacturing conditions, leading to excessive erase pulses being applied to devices that have already completed erasure, complicating the testing apparatus and extending test time.
Innovation Solution
Incorporating a flag circuit and an erase prohibition circuit in the operation control circuit of non-volatile semiconductor memory devices to prevent erase operations when all memory cells have completed erasure, ensuring that erase commands or voltages are only applied when incompletion is detected, thereby avoiding unnecessary operations during simultaneous testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simultaneous erase testing is performed on multiple non-volatile semiconductor memory devices, then testing productivity is improved, but unnecessary erase operations are executed on devices that have already completed erasure, leading to wasted time and energy
Solution Approach 1:
The flag circuit performs a preliminary action by setting a flag signal before the erase verify operation to indicate that erase operations should be prohibited. This preliminary setting allows the erase prohibition circuit to immediately prevent unnecessary erase operations when all memory cells have completed erasure, thereby avoiding wasted time and energy while maintaining high testing productivity across multiple devices
Solution Approach 2:
The flag circuit receives feedback from the erase verify operation about the erasure completion status of memory cells. Based on this feedback, the flag circuit sets or resets the flag signal, which then controls the erase prohibition circuit. This feedback mechanism ensures that erase operations are only executed when necessary, preventing time waste while maintaining efficient simultaneous testing
2Reliability
If erase operations are continuously applied to all devices until maximum erase times are reached, then all devices are tested uniformly, but devices that have completed erasure receive excessive erase pulses, complicating the testing apparatus
Solution Approach 1:
The flag circuit and erase prohibition circuit form a self-service mechanism within the memory device itself. The flag circuit automatically sets or resets the flag signal based on the erasure completion status detected during erase verify operations. This self-service approach eliminates the need for complex external control logic in the testing apparatus, as the device autonomously manages its own erase operation status and prohibits unnecessary operations
Solution Approach 2:
The erase prohibition function is extracted from the external testing apparatus and integrated into the memory device's internal operation control circuit. By taking out the complexity from the external apparatus and embedding it within the device itself through the flag circuit and erase prohibition circuit, the testing apparatus remains simple while achieving reliable and efficient testing
Data Source
AI summary
A non-volatile semiconductor memory device includes a memory cell array and an operation control circuit. The memory cell array includes a plurality of non-volatile memory cells that are electrically rewritable. The operation control circuit controls an operation of the memory cell array in accordance with an external instruction. The operation control circuit includes a flag circuit and an erase prohibition circuit. The flag circuit is set when erase incompletion is detected from any of the memory cells by an erase verify operation of the memory cell array. The erase prohibition circuit prohibits an erase operation to the memory cell array irrespective of the external instruction when the flag circuit is in a reset state.