Shared Sense Amplifier for Read-While-Write Memory
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Solution Overview
Problem
Existing memory technologies face inefficiencies in writing memory states due to longer processes compared to reading, and replicating sense circuitry for read-while-write (RWW) capabilities can be costly and complex, leading to inactivated partitions and increased complexity in decoding signals.
Innovation Solution
Implementing a RWW architecture with common sense circuitry across multiple partitions, utilizing dual path decoding and P-type FETs to reduce semiconductor area and improve power efficiency, allowing concurrent reading and writing operations while minimizing additional complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sense circuitry is replicated for each partition to enable RWW capability, then concurrent read and write operations can be performed, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a single sense amplifier that can be dynamically shared between read and write operations across multiple partitions. The sense amplifier is controlled by partition select signals that route it to different partitions based on the current operation type, allowing one amplifier to perform multiple functions that would traditionally require separate dedicated amplifiers for each partition.
Solution Approach 2:
The patent merges the sense amplifier resources across multiple partitions by implementing a shared sense amplifier architecture. Instead of having separate sense amplifiers for each partition, the design combines them into a single shared resource that is time-multiplexed and space-multiplexed across partitions through controlled switching and signal routing.
2Productivity
If separate sense circuitry is implemented for each partition, then RWW operations are enabled, but semiconductor area increases
Solution Approach 1:
The sense amplifier is designed as a universal resource that can serve multiple partitions through dynamic configuration. Control logic and partition select signals enable the same physical sense amplifier to be assigned to different partitions based on operational requirements, eliminating the need for separate dedicated amplifiers in each partition and thereby reducing the total semiconductor area required.
Solution Approach 2:
The patent introduces temporal and spatial multiplexing dimensions to the sense amplifier usage. By controlling which partition accesses the sense amplifier at different times and under different conditions, the system effectively expands the utility of a single amplifier across multiple partitions without requiring additional physical space for separate amplifiers in each partition.
3Device complexity
If more partitions remain inactivated to accommodate RWW architecture, then sense circuitry complexity is reduced, but productivity decreases
Solution Approach 1:
The patent implements dynamic control of the sense amplifier through partition select signals and control logic that can rapidly switch the amplifier's assignment between different partitions. This dynamic allocation allows the system to maintain low circuitry complexity while achieving concurrent read-write operations across multiple partitions, as the sense amplifier is actively routed to the required partition based on real-time operational demands.
Solution Approach 2:
The system changes the operational parameters of the sense amplifier by adjusting its assigned partition through control signals. By modifying which partition the sense amplifier monitors or writes to, the system enables flexible concurrent operations without requiring the amplifier structure itself to change, thereby maintaining simplicity while improving productivity.
Data Source
AI summary
A plurality of block configurations may be employed for read while write operations. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.