NAND Flash Page Buffer Voltage Control Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current NAND flash memory devices face challenges in precise current sensing due to the all-bit-line scheme, which requires maintaining constant voltage on bit-lines, leading to reduced read current and compromised sensing precision, and also suffers from increased read time and noise in parallel sensing operations.
Innovation Solution
A page buffer circuit with specific switching circuits and voltage control mechanisms that allow for pre-charging and discharging of bit-lines during sensing operations, maintaining voltage levels across bit-lines and reducing recovery time, thereby enhancing sensing precision and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If constant voltage is maintained on bit-lines during parallel sensing operations, then sensing stability is improved, but read current is reduced and sensing precision is compromised
Solution Approach 1:
The patent applies periodic action by dividing the sensing operation into distinct phases: a pre-charge period where bit-lines are charged to a first voltage level, an evaluation period where sensing occurs, and a recovery period where bit-lines are recharged. This periodic voltage application allows the bit-lines to maintain adequate voltage levels during sensing while enabling recovery between operations, thereby preserving both sensing precision and operational reliability
Solution Approach 2:
The patent implements preliminary action by pre-charging the bit-lines to a first voltage level before the sensing operation begins. This pre-charge ensures that sufficient voltage is available at the start of the evaluation period, enabling accurate sensing of the read current without requiring constant voltage maintenance throughout the entire operation cycle
2Productivity
If parallel sensing operations are performed on all bit-lines, then throughput is improved, but read time is increased and noise is generated
Solution Approach 1:
The patent uses periodic action to structure parallel sensing operations into repeated cycles of pre-charge, evaluation, and recovery periods. This allows multiple bit-lines to be sensed in parallel during evaluation periods while systematically managing the timing of operations to minimize total read time and reduce noise through controlled operation sequencing
Solution Approach 2:
The patent segments the sensing operation into distinct time periods (pre-charge period, evaluation period, recovery period) and applies different voltage conditions to different groups of bit-lines in different periods. This segmentation allows parallel operations to proceed efficiently while managing resource contention and noise through temporal and spatial division
3Measurement precision
If voltage is maintained on bit-lines during recovery period, then sensing precision is preserved, but energy consumption is increased
Solution Approach 1:
The patent applies periodic action by maintaining voltage on bit-lines only during specific periods (pre-charge and evaluation periods) while allowing voltage to be reduced or removed during the recovery period. This periodic voltage application preserves sensing precision when needed while reducing energy consumption during non-sensing intervals
Solution Approach 2:
The patent implements discarding and recovering by intentionally allowing bit-line voltage to discharge during the recovery period after sensing is complete, then recovering the voltage in the next pre-charge period. This approach discards the voltage during periods when it is not needed for sensing, thereby reducing energy consumption while maintaining precision during active sensing operations
Data Source
AI summary
A page buffer circuit may include: a first node; a first switching circuit configured to pre-charge the bit-line based on a voltage provided to the first switching circuit; a sensing node; a second switching circuit configured to discharge the sensing node when the voltage value of the first node is lower than a voltage value associated with a voltage inputted to the second switching circuit during an evaluation period; a sense latch configured to latch a voltage being determined based on the voltage level of the sensing node, during a strobe period; and a third switching circuit configured to prevent the voltage value of the first node from being lower than a voltage value associated with a voltage inputted to the third switching circuit independently from the voltage at the sense latch.