NAND Flash Memory Power Loss Data Backup

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Solution Overview

Problem

During the programming of NAND flash memory, abrupt power loss can result in the loss of lower page data, which is critical for maintaining the integrity and functionality of memory systems, especially in vehicles where system reliability and safety are paramount.

Innovation Solution

A differential storage device with associated logic is used to automatically initiate a backup of prior page data when a power loss is detected, allowing for the preservation of data states with minimal changes in threshold voltage, thereby eliminating the need for verify operations and energy storage devices like hold-up capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional programming methods are used without backup mechanisms, then programming speed is maintained, but data integrity is lost during power loss events

Engineering Contradiction:
Improvedata integrityVSAvoidprogramming mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by detecting power loss conditions and initiating backup programming of lower page data to a safe location before the power loss completes. The system monitors power status and preemptively saves critical data that would otherwise be lost, ensuring data integrity without requiring complex post-failure recovery mechanisms.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If hold-up capacitance is added to maintain power during programming, then data integrity is preserved, but device complexity and cost increase

Engineering Contradiction:
Improvedata integrityVSAvoidenergy storage requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the energy storage function from the main programming system by using a separate, minimal capacitance element dedicated solely to detecting power loss conditions. This extracted approach allows the system to maintain data integrity through detection and responsive backup programming rather than requiring large hold-up capacitance to sustain the entire programming operation during power failures.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary detection mechanism that mediates between the power supply and the programming operation. This intermediary monitors power status and triggers appropriate backup actions, serving as a lightweight bridge that preserves data integrity without requiring the power supply to directly sustain the programming operation through large energy storage elements.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If verify operations are implemented to ensure data integrity, then reliability improves, but programming time increases

Engineering Contradiction:
Improvedata verificationVSAvoidprogramming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing verification during the backup programming process itself. Rather than separating verification into a distinct post-programming step, the system verifies data integrity as part of the power-loss recovery backup operation, combining protection and verification functions to minimize additional time overhead.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3676838B1Responding to power loss
Publication Date: 2022.11.23 MICRON TECHNOLOGY INC
  • EP3676838B1 patent drawingFigure 1A
  • EP3676838B1 patent drawingFigure 1B
  • EP3676838B1 patent drawingFigure 2A

AI summary

Methods of operating memory, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of the memory, programming additional data to the particular memory cell, determining if a power loss to the memory is indicated while programming the additional data to the particular memory cell, and, if a power loss to the memory is indicated, selectively programming one memory cell of a pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell. A resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells is representative of the information indicative of the data value stored in the particular memory cell.