Blocking Dielectric in Etch Stop Tier for 3D Memory

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Solution Overview

Problem

The fabrication of 3D semiconductor devices with multiple stacked tiers and high aspect ratio openings poses challenges such as undercut and delamination issues when exposed to chemicals like Hot Phosphoric Acid and Hydrofluoric Acid, particularly with etch stop layers like Aluminum Oxide (ALOX) being sensitive to these acids.

Innovation Solution

Incorporating a blocking dielectric, such as silicon oxide, adjacent to the etch stop tier and using dielectric films that extend into the etch stop tier to prevent undercut and delamination, and employing a backfill oxide to protect the etch stop layer from these acids, thereby allowing reliable nitride removal and improved control over recesses and deposition profiles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If etch stop layer (ALOX) is exposed to Hot Phosphoric Acid and Hydrofluoric Acid for nitride removal, then nitride can be removed, but undercut and delamination issues occur due to acid sensitivity

Engineering Contradiction:
Improvenitride removal reliabilityVSAvoidacid corrosion damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A blocking dielectric layer is introduced as an intermediary between the etch stop layer and the corrosive acids. This blocking dielectric is resistant to Hot Phosphoric Acid and Hydrofluoric Acid, allowing nitride removal to proceed while preventing the acids from attacking and damaging the etch stop layer, thus eliminating undercut and delamination issues

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric structure is segmented into multiple functional layers: the original etch stop layer (ALOX) and an additional blocking dielectric layer. This segmentation allows each layer to perform its specific function - the etch stop layer provides etch selectivity while the blocking dielectric provides chemical resistance during acid-based nitride removal

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple stacked tiers with high aspect ratio openings are fabricated, then device capacity and integration are improved, but fabrication complexity and process control difficulty increase

Engineering Contradiction:
Improvedevice capacityVSAvoidfabrication process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by making the dielectric structure compositionally heterogeneous - different dielectric materials are used in different regions/layers. The blocking dielectric is specifically placed where acid exposure occurs during nitride removal, providing localized chemical resistance exactly where needed, while other regions maintain their original etch stop properties

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The blocking dielectric layer is formed in advance before the acid-based nitride removal process. This preliminary action ensures that the protective layer is already in place to prevent undercut and delamination issues before they can occur during subsequent fabrication steps

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces undercut and delamination issues, enabling reliable nitride removal and enhancing data retention and cycling reliability in 3D semiconductor devices by protecting the etch stop layer from corrosive acids.

Implementation Method 1

Incorporating a blocking dielectric, such as silicon oxide, adjacent to the etch stop tier and using dielectric films that extend into the etch stop tier to prevent undercut and delamination, and employing a backfill oxide to protect the etch stop layer from these acids

Methodology Applied
Scientific EffectChemical resistance:

Data Source

PatentUS10847527B2Memory including blocking dielectric in etch stop tier
Publication Date: 2020.11.24 MICRON TECHNOLOGY INC
  • US10847527B2 patent drawing
  • US10847527B2 patent drawing
  • US10847527B2 patent drawing

AI summary

Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.