Transistor TRIZ Cases

A semiconductor capacitor uses a helical first electrode with a spiral groove to expand surface area and increase capacitance.

Amorphous multi-component metallic films provide homogeneous electrode surfaces for metal-insulator-metal diode structures.

Lateral well width controls the JFET pinch-off voltage, resolving fabrication precision issues caused by difficult depth measurements.

Selective wet etching of sacrificial sublayers controls recess depth without plasma damage, enabling accurate threshold voltage tuning.

Segmented epitaxial and ion implantation stages create gradient buffer layers that improve collector injection efficiency while minimizing stored charge.

A dual-layer gate insulating layer combines a sol-gel first layer with an inorganic or organic polymer second layer to enhance the dielectric constant.

Buried insulating layers suppress parasitic bipolar transistor formation, enabling high-density integration of same-conductivity transistors on one substrate.

Recessed conductive regions in a 3D field plate structure relax peak electric fields to increase breakdown voltage from 880 V to 1360 V.

Increasing adhesive thickness to 30 micrometers traps foreign matter, preventing substrate protrusions that damage array circuit layers.

A continuous cell pillar eliminates pinch-points in 3D memory stacks.

A semiconductor floating gate stores electrons to retain data in one-time programming memory.

Selecting <110> crystallographic orientation for pre-amorphized transistor regions eliminates stacking faults that degrade leakage current and reliability.

Segmented cylindrical electrodes and sandwiched conductive layers increase capacitance while eliminating etch depth limitations and electrical shorts.

A transistor with embedded sigma shaped semiconductor alloy induces strain in the channel region to enhance charge carrier mobility.

A protection circuit uses transistors to divert electrostatic discharge from signal input lines in organic light emitting displays.

An insulating film with excess oxygen supplies oxygen atoms to the oxide semiconductor film, preventing leakage current and stabilizing threshold voltage.

A BJT ESD clamp adjusts breakdown voltage by masking part of the n-collector to reduce charge carriers available for avalanche multiplication.

A III-N MOSFET forms on a silicon fin sidewall using a compliant epitaxial template to reduce defect densities in the semiconductor channel.

A silicide layer separates the contact from doped polysilicon in a deep trench capacitor structure.

High energy ion implantation creates deep junction isolation features in silicon carbide epitaxial layers.

A clocked energy regulator buffers switching peaks in a DC-DC converter.

Air gaps in sidewall spacers lower the effective dielectric constant, reducing parasitic capacitance and signal delays.

Floating gates adjoin active region sidewalls to resolve leakage current and insufficient control gate space trade-offs in nonvolatile memory devices.

Phosphorous doped hemispherical grain polysilicon capacitors reduce depletion ratios below 10 percent, maintaining consistent capacitance across voltage biases.

A light-blocking pattern positioned between the base substrate and active pattern blocks external radiation from reaching the channel layer.

A buried gate liner with a metal alloy gradient reduces leakage current by lowering the work function near source/drain regions.

Selective full metal gate materials modulate threshold voltage without channel doping, resolving integration complexity in sub-20nm SoC designs.

A liquid crystal display pixel electrode uses an insulation layer with convexities to increase reflection area.

A FinFET fabrication method uses local quality to manage isolation layer stress differences across trenches of varying widths.

Microwave radiation forms low-resistance ternary alloy contacts, reducing electrical resistance at metal interfaces.

Collector ballast resistor layer suppresses avalanche multiplication in heterojunction bipolar transistors.

A self-aligned bottom contact structure aligns with the gate in vertical field effect transistors.

Nitrided niobium nitride lower electrode supports a tetragonal hafnium oxide dielectric layer to maintain capacitance in downscaled semiconductor devices.

A switching element drive device dynamically adjusts gate drive voltage based on load current and input voltage measurements.

Low-temperature heating creates thermal stress to separate the silicon thin film, preventing breakage and cracks caused by high-temperature processing.

An air gap isolates the gate electrode from the cap layer edge in an InP HEMT mesa structure.

A charging circuit recharges bootstrap capacitance using back electromotive force voltage spikes from an inertial load.

A field transistor structure integrates a polysilicon layer and thin metal portions to enable multiple circuit functions within standard foundry processes.

A gate drive apparatus uses a coil and clamp switch to control switching element voltage.

An intermediary silicon oxide layer shields the aluminum oxide etch stop tier from hot phosphoric acid damage, preventing undercut and delamination.

A nonvolatile semiconductor memory device uses segmented charge storage regions separated by insulating barriers within a laminated pillar structure.

A thin-film semiconductor device uses an aluminum oxide protection layer with controlled film density to embed extraction electrodes.

A mesa semiconductor device uses a second insulation film to cover anode electrode end portions within a deep mesa groove.

A gate-all-around semiconductor structure adjusts threshold voltage through controlled lateral dimensions of high-k metal gates.

A metal gate stack with multiple barrier layers protects high-k dielectrics from plasma damage during deposition.

Microvoids in oxide semiconductor source and drain regions capture hydrogen atoms, preventing threshold voltage shifts and stabilizing electric characteristics.

Insulator patterns between fins suppress the short channel effect for better electric potential control.

A reverse conducting IGBT uses a lattice-pattern trench gate in the IGBT region and a stripe-pattern trench member in the diode region.

A level shifting circuit with a protection network isolates switch nodes to prevent leakage currents during power down.