III-N Transistor Monolithic Integration via Selective Etching
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Solution Overview
Problem
Current dry plasma etching techniques for forming gate recesses in III-Nitride transistors suffer from plasma-induced damage and etch-based process variations, making it difficult to control recess depth and achieve precise control over transistor parameters such as transconductance and threshold voltage, especially when integrating transistors with different threshold voltages on a common substrate.
Innovation Solution
The use of multi-layer semiconductor structures with selectively etchable sublayers allows for precise control of etching depth and reduces defect density, employing a combination of dry and wet etching techniques to form gate and ohmic recesses, enabling the monolithic integration of III-Nitride transistors with different threshold voltages on a common substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dry plasma etching is used to form gate recesses, then the etching process can be performed on III-Nitride materials, but plasma-induced damage occurs and etch-based process variations make it difficult to control recess depth precisely
Solution Approach 1:
A sacrificial layer is introduced as an intermediary between the gate electrode and the AlGaN/GaN heterostructure. This sacrificial layer enables wet chemical etching to be used instead of plasma etching, as it provides a layer that can be selectively removed by wet etchants. The sacrificial layer mediates the etching process, allowing precise depth control without exposing the underlying III-Nitride materials to damaging plasma conditions.
Solution Approach 2:
The patent replaces the plasma-based dry etching process with a wet chemical etching process. This substitution eliminates the harmful plasma effects while maintaining the ability to form gate recesses. The wet etching process uses chemical solutions to remove the sacrificial layer, providing better control over etching depth and reducing process variations.
2Reliability
If dry plasma etching is used for gate recess formation, then the process can be completed in a single step, but etch-based process variations cause variation in transistor parameters such as transconductance and threshold voltage
Solution Approach 1:
The sacrificial layer serves as a mediator that decouples the gate recess formation from the underlying heterostructure. By etching the sacrificial layer with wet chemicals rather than plasma, the process becomes more uniform and controllable. The sacrificial layer acts as a buffer that absorbs etching variations, preventing them from directly affecting the transistor parameters.
Solution Approach 2:
The patent changes the etching methodology from plasma-based to chemistry-based wet etching. This parameter change in the etching process fundamentally alters the mechanism of material removal, leading to better uniformity and reduced process variations. The wet etching chemistry can be precisely controlled to achieve consistent etching rates and depths across different devices.
3Adaptability or versatility
If monolithic integration of III-N transistors with different threshold voltages is achieved, then design flexibility and performance are improved, but precise control of threshold voltages requires complex fabrication processes
Solution Approach 1:
The patent segments the gate stack into distinct functional layers: the AlGaN/GaN heterostructure, the sacrificial layer, and the gate electrode. This segmentation allows independent optimization and control of each layer. The sacrificial layer segmentation enables different etching depths to be achieved for different devices, allowing integration of transistors with different threshold voltages using a standardized fabrication process.
Solution Approach 2:
The sacrificial layer enables local quality control in the gate recess formation. By controlling the etching depth locally for different device regions, transistors with different threshold voltages can be created on the same substrate. Each device can have its gate recess depth precisely controlled to achieve the desired threshold voltage, while using the same overall fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the precise control of recess depths and low defect densities, facilitating the flexible integration of multiple transistors with varying gate and ohmic recess depths, thereby achieving accurate and flexible control of threshold voltages, improving the performance and design flexibility of integrated circuits.
Implementation Method 1
employing a combination of dry and wet etching techniques to form gate and ohmic recesses
Implementation Method 2
Chlorine-based dry plasma etching is typically used to form gate recesses in AlGaN/GaN devices, as both GaN and AlGaN are very inert to wet chemical etchants. However, dry plasma etching is prone to plasma-induced damage
Data Source
AI summary
Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a material AlxInyGazN (0≦x, y, z≦1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0<z≦1). A gate recess is disposed in a number of adjacent sublayers of the cap layer to achieve a desired threshold voltage for a transistor. Also described are methods for fabricating such semiconductor structures, where gate recesses and/or ohmic recesses are formed by selectively removing adjacent sublayers of the cap layer. The performance of the resulting integrated circuits is improved, while providing design flexibility to reduce production cost and circuit footprint.