High Energy Ion Implantation for SiC Junction Isolation
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Solution Overview
Problem
Wide-bandgap semiconductor materials like silicon carbide (SiC) present challenges in device design and fabrication due to differences from silicon (Si) material systems, making existing electrical isolation techniques unsuitable for SiC integrated circuits, particularly in achieving effective electrical isolation between transistors.
Innovation Solution
The use of high-energy ion implantation to form junction isolation features in SiC epitaxial layers, followed by annealing, which allows for deeper and narrower electrical isolation, simplifying the fabrication process and improving packing density compared to trench isolation methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trench isolation methods are used in SiC devices, then electrical isolation between transistors is achieved, but fabrication complexity and cost increase due to multiple processing steps
Solution Approach 1:
The patent extracts the isolation function from the complex trench isolation process and implements it through a simplified junction isolation approach using ion implantation, removing unnecessary processing steps while maintaining electrical isolation effectiveness
Solution Approach 2:
The patent replaces the mechanical trench formation and filling process with an ion implantation process that directly creates the isolation junction, substituting a simpler physical process for a complex multi-step mechanical fabrication sequence
2Reliability
If junction isolation features are formed deeper in SiC epitaxial layers, then electrical isolation effectiveness improves, but fabrication difficulty increases
Solution Approach 1:
The patent changes the energy parameter of ion implantation to achieve deeper junction isolation features, using high energy (e.g., 2.0 MeV) to penetrate deeper into the SiC epitaxial layer and create effective isolation at greater depths without increasing fabrication complexity
3Productivity
If high-energy ion implantation is used to form deep junction isolation features, then packing density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs feedback control in the ion implantation process, using in-situ monitoring and post-implantation characterization to verify and adjust implantation parameters, ensuring precise depth control while maintaining high packing density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective electrical isolation between transistors in SiC integrated circuits, allowing for deeper junction isolation features, reduced fabrication steps, and improved packing density, while maintaining planarity and reducing time and cost.
Implementation Method 1
forming a junction isolation feature between or around the adjacent planar devices by implanting dopants in the epitaxial SiC layer via high-energy ion implantation
Implementation Method 2
The method also includes annealing the junction isolation feature
Data Source
AI summary
An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (μm).