Transistor Shallow Junctions Crystal Orientation Defect Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fabrication of highly scaled transistors with ultra-shallow PN junctions faces challenges due to the generation of crystalline defects during the re-crystallization process, which affects the performance and reliability of integrated circuits, particularly in CMOS technology, where reducing channel length increases leakage current and degrades transistor performance.
Innovation Solution
The method involves aligning the crystallographic orientation of the semiconductor material to match growth directions during re-crystallization, reducing the formation of stacking faults and crystalline defects by selecting appropriate Miller indices for the semiconductor layer, allowing for efficient formation of shallow PN junctions with minimal defects through pre-amorphization and re-crystallization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pre-amorphization implantation is performed to form ultra-shallow PN junctions, then the vertical position control and dopant profile precision are improved, but crystalline defects are generated during re-crystallization
Solution Approach 1:
The patent changes the crystallographic orientation parameter of the semiconductor substrate from conventional <100> to <110>. This parameter change fundamentally alters the re-crystallization behavior after pre-amorphization implantation, enabling the formation of ultra-shallow PN junctions with superior crystalline quality and minimal defects.
Solution Approach 2:
The patent employs a composite approach by combining specific crystallographic orientation (<110>) with controlled pre-amorphization implantation and re-crystallization processes. This composite methodology creates optimal conditions for forming ultra-shallow junctions while maintaining high crystalline quality.
2Speed
If channel length is reduced to increase operating speed, then the operating speed is improved, but leakage current increases and gate controllability degrades
Solution Approach 1:
By changing the crystallographic orientation to <110> and optimizing the re-crystallization process, the patent achieves ultra-shallow PN junctions with precisely controlled vertical positions. This enables shorter channel lengths to be implemented while maintaining effective gate controllability and reducing leakage current through improved junction depth control.
3Manufacturing precision
If sophisticated implantation techniques are used to create shallow drain and source regions, then the channel controllability is improved, but the process complexity increases
Solution Approach 1:
The patent simplifies the implantation process by changing the substrate orientation to <110>. This parameter change naturally favors shallower implantation profiles and reduces the need for highly sophisticated multi-step implantation techniques, thereby maintaining channel controllability while reducing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the crystalline quality of channel and adjacent regions, reducing leakage current and improving transistor performance by minimizing crystalline defects, thereby enabling the formation of sophisticated transistor devices with enhanced reliability and efficiency.
Implementation Method 1
the semiconductor layer is annealed to re-crystallize the substantially amorphized portion
Implementation Method 2
performing an amorphization implantation process for forming a substantially amorphized region in the initially crystalline semiconductor layer
Data Source
AI summary
By appropriately adapting the length direction and width directions of transistor devices with respect to the crystallographic orientation of the semiconductor material such that identical vertical and horizontal growth planes upon re-crystallizing amorphized portions are obtained, the number of corresponding stacking faults may be significantly reduced. Hence, transistor elements with extremely shallow PN junctions may be formed on the basis of pre-amorphization implantation processes while substantially avoiding any undue side effects typically obtained in conventional techniques due to stacking faults.