Self-Aligned Bottom Contact for Vertical Transistor Alignment
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Solution Overview
Problem
In the fabrication of vertical field effect transistors (VFETs) for SRAM circuits, existing technologies face challenges with lithography variations leading to misaligned bottom contacts, which can cause circuit failures due to limited design area and overlap issues, resulting in inefficiencies and potential short circuits.
Innovation Solution
The implementation of a self-aligned bottom contact (BC) scheme that accounts for lithography variations, ensuring the BC is aligned with the gate, preventing overlap and circuit failures, through a process involving epitaxial growth, silicide formation, and specific spacer and dielectric layer deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography alignment methods are used for bottom contact formation, then manufacturing process simplicity is maintained, but manufacturing precision deteriorates due to lithography variations causing misalignment
Solution Approach 1:
The method performs preliminary actions by forming the bottom contact before patterning the gate, and using the gate pattern itself as the alignment reference for subsequent steps. This preliminary sequencing eliminates the need for separate alignment processes and ensures automatic alignment between the bottom contact and gate, resolving the contradiction between precision and complexity.
2Productivity
If design area is reduced for tight cell layouts, then productivity increases, but manufacturing precision deteriorates due to overlap issues and circuit failures
Solution Approach 1:
The invention transitions from planar 2D layout constraints to 3D vertical stacking, where the bottom contact is formed in a lower layer and the gate is formed above it. This dimensional change allows tight cell layouts with high device density while maintaining precise alignment through the self-aligned process, eliminating overlap issues that plague conventional 2D layouts.
3Reliability
If self-aligned bottom contact scheme is implemented, then manufacturing precision improves by preventing misalignment, but device complexity increases due to additional process steps
Solution Approach 1:
The gate pattern serves as its own alignment reference for the bottom contact formation. The self-aligned process uses the gate structure itself to define the precise location of the bottom contact, eliminating the need for separate alignment procedures and reducing process complexity while improving reliability.
4Reliability
If conventional contact formation is used, then device complexity is minimized, but reliability deteriorates due to misalignment and potential short circuits
Solution Approach 1:
The bottom contact is formed in advance before gate patterning, using the subsequent gate pattern as the alignment template. This preliminary action ensures that the contact is automatically positioned correctly relative to the gate, preventing misalignment and short circuits while maintaining process simplicity through sequential rather than concurrent operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-aligned BC design enhances the reliability of VFET SRAM circuits by preventing misalignment and overlap, thereby improving device performance and reducing the risk of circuit failures, even in tight cell designs, by ensuring precise contact formation.
Implementation Method 1
a first vertical fin connected to a gate and a first doped region, wherein the first doped region is formed on a substrate
Implementation Method 2
a second vertical fin connected to the gate and a source or a drain (S/D), wherein the S/D is formed on the substrate
Data Source
AI summary
According to an embodiment of the present invention, a semiconductor device includes a plurality of transistors, wherein each of the plurality of transistors includes a first vertical fin connected to a gate and a first doped region, wherein the first doped region is formed on a substrate, a second vertical fin connected to the gate and a source or a drain (S/D), wherein the S/D is formed on the substrate and a bottom contact self-aligned with and connected to the gate and a second doped region. Each of the plurality of transistors is operably connected to form the semiconductor device.