Silicided Deep Trench Decoupling Capacitor Parasitic Resistance

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Solution Overview

Problem

Deep trench capacitors in semiconductor structures suffer from parasitic resistance issues that adversely affect the semiconductor structure, which existing technologies have not adequately addressed.

Innovation Solution

A semiconductor structure and method involving a trench capacitor with a dielectric liner layer, a doped polysilicon layer, and a silicide layer, where the silicide layer separates the contact from the doped polysilicon layer, and a contact is formed with a lower surface not abutting the silicide layer, reducing parasitic resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a deep trench capacitor structure is used for decoupling, then electrical noise diversion capability is improved, but parasitic resistance increases adversely affecting the semiconductor structure

Engineering Contradiction:
Improvenoise diversion capabilityVSAvoidparasitic resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The capacitor structure is divided into multiple functional segments: a first conductive layer forming the bottom electrode, a dielectric layer, and a second conductive layer forming the top electrode. This segmentation allows optimization of each layer's properties to reduce parasitic resistance while maintaining noise diversion capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs composite material structures including silicide layers combined with conductive layers, and multi-layer dielectric compositions. These composite materials provide both low resistance pathways and effective electrical isolation, reducing parasitic resistance while maintaining the decoupling function.

Inventive Principle:
Principle #40Composite materials

2Ease of manufacture

If existing trench capacitor structures are used, then manufacturing simplicity is maintained, but parasitic resistance issues are not adequately addressed

Engineering Contradiction:
Improvestructure simplicityVSAvoidparasitic resistance
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

Silicide layers are formed on the conductive layers before final contact formation. This preliminary silicide formation reduces contact resistance in advance, ensuring low parasitic resistance is achieved before subsequent manufacturing steps without adding significant process complexity.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If the contact directly contacts the doped polysilicon layer, then manufacturing steps are reduced, but parasitic resistance increases

Engineering Contradiction:
Improvenumber of layersVSAvoidparasitic resistance
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

A silicide layer is introduced as an intermediary between the contact and the doped polysilicon layer. This silicide layer provides a low-resistance pathway for current flow, reducing parasitic resistance while the contact structure maintains manageable complexity through standardized contact formation processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces parasitic resistance in deep trench capacitors, improving the performance of decoupling capacitors and minimizing adverse effects on the semiconductor structure.

Implementation Method 1

a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer

Methodology Applied
Scientific EffectElectrical Conduction: Conduction (electrical)

Implementation Method 2

a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9385179B2Deep trench decoupling capacitor and methods of forming
Publication Date: 2016.07.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9385179B2 patent drawing
  • US9385179B2 patent drawing
  • US9385179B2 patent drawing

AI summary

Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a method of forming a semiconductor device includes: forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate; depositing a dielectric liner layer inside the trench; depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate; forming a silicide layer over a portion of the doped polysilicon layer; forming an intermediate contact layer within the inner trench; and forming a contact over a portion of the intermediate contact layer and a portion of the silicide layer.