Hemispherical Grain DRAM Capacitor Depletion Ratio Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor integrated circuit capacitors exhibit high depletion ratios due to variations in capacitance values when biased with positive and negative voltages, leading to reduced storage performance and frequent charge refresh requirements, especially in DRAM applications.
Innovation Solution
A method involving the formation of hemispherical grains on a polysilicon layer, followed by phosphorous doping in specific temperature and pressure conditions, and subsequent rapid thermal oxidation and nitridation processes to create a low depletion ratio capacitor, with an alumina film deposition to enhance surface area and reduce capacitance variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capacitor structures are used in DRAM, then manufacturing is simpler, but depletion ratio is high causing capacitance variation
Solution Approach 1:
The patent applies hemispherical grain structure to the polysilicon lower electrode, transforming the flat surface into a curved spherical surface. This curvature increases the effective surface area by approximately 39% compared to a flat surface, thereby increasing capacitance while maintaining the same footprint. The spherical geometry also promotes uniform electric field distribution, reducing depletion effects and improving capacitance consistency across positive and negative biases.
Solution Approach 2:
The patent implements a multi-layer nested structure where the hemispherical grain polysilicon lower electrode is nested within a trench, which is further nested within a dielectric layer containing an alumina film, which is then nested within an upper electrode structure. This nested arrangement maximizes the use of vertical space to increase effective capacitor surface area without increasing the planar footprint, thereby improving capacitance consistency without excessive complexity.
2Quantity of substance
If capacitor surface area is increased to improve charge storage, then charge storage capacity increases, but device footprint increases
Solution Approach 1:
The patent transitions from a two-dimensional planar capacitor structure to a three-dimensional hemispherical grain structure. By utilizing the vertical dimension and creating spherical grains within the polysilicon layer, the effective surface area is increased by approximately 39% without increasing the planar footprint. This dimensional transformation allows more charge storage capacity within the same device area.
Solution Approach 2:
The hemispherical grain structure creates a curved surface that packs more surface area into the same footprint compared to a flat surface. The spherical geometry naturally provides approximately 39% more surface area than a flat plane of the same footprint, enabling increased charge storage capacity without expanding the device area.
3Reliability
If rapid thermal oxidation is applied to doped HSG polysilicon, then depletion ratio is reduced, but process complexity increases
Solution Approach 1:
The patent performs phosphorous doping of the hemispherical grain polysilicon structure before applying rapid thermal oxidation. This preliminary doping action is crucial because it establishes the appropriate carrier concentration and electrical properties in the lower electrode before the oxidation process. The pre-doped structure then responds more favorably to the rapid thermal oxidation, achieving better depletion ratio reduction while managing process complexity through proper sequencing.
Solution Approach 2:
The patent utilizes rapid thermal oxidation to change the physical and chemical parameters of the doped polysilicon surface. The high-temperature oxidation process modifies the surface properties, reduces depletion effects, and improves capacitance consistency. By controlling oxidation time and temperature parameters, the process achieves reliable depletion ratio reduction while keeping the process complexity manageable through precise parameter control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves a low depletion ratio of less than 10, improving capacitor performance by maintaining a consistent capacitance value across voltage biases, reducing leakage current, and enhancing breakdown voltage, while being compatible with conventional fabrication processes.
Implementation Method 1
doping the HSG formed polysilicon in a 200 Torr pressure gas atmosphere containing phosphine (PH3) at a temperature in the range of 600° C. to 700° C.
Implementation Method 2
doping the HSG formed polysilicon in a 200 Torr pressure gas atmosphere containing phosphine (PH3) at a temperature in the range of 600° C. to 700° C.
Implementation Method 3
a rapid thermal oxidation process after phosphorous doping of a hemispherical grained poly-silicon film
Implementation Method 4
nitridizing the doped HSG polysilicon
Implementation Method 5
an alumina film deposition to enhance surface area and reduce capacitance variation
Data Source
AI summary
A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.