Full Metal Gate Integration for Multiple Threshold Voltage Control

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Solution Overview

Problem

Scaling bulk technology beyond the 20 nm node faces challenges in low power applications due to competing requirements of density, power, and performance, and increased device variation and parasitics, particularly in achieving optimal tradeoff between power and performance in System-on-chip (SoC) applications, where landing contacts correctly becomes difficult and multiple threshold voltage is required for fully depleted devices like ETSOI or FinFETs, which cannot be achieved through channel doping.

Innovation Solution

The integration of multiple threshold voltage devices using full metal gate technology, which enables self-aligned contacts and Vt modulation through materials and process adjustments, eliminating the need for channel doping and ground plane/back gate, and allowing for simple gate-first integration, extending to planar PDSOI and FinFET technologies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If channel doping is used to achieve multiple threshold voltages, then Vt modulation is possible, but device complexity and integration challenges increase

Engineering Contradiction:
Improvemultiple threshold voltage capabilityVSAvoidintegration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by depositing different metal gate materials (such as TiN, TaN, WN) selectively over different regions corresponding to n-type and p-type transistors. This allows each transistor type to have locally optimized work function and threshold voltage without requiring channel doping, thereby achieving multiple Vt values while reducing device complexity and integration challenges.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If self-aligned contacts are implemented, then contact landing precision improves, but manufacturing process complexity increases

Engineering Contradiction:
Improvecontact landing precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent implements preliminary action by forming the metal gate stack structure before contact formation. The metal gate material serves as a preliminary structure that defines the contact location, allowing self-aligned contacts to be formed subsequently without requiring precise manual alignment, thereby improving contact landing precision while managing process complexity through sequential fabrication steps.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If ground plane and back gate are used for Vt control, then Vt modulation is achieved, but device structure and integration become more complex

Engineering Contradiction:
ImproveVt control capabilityVSAvoidstructure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts the Vt control function from the traditional ground plane and back gate structures and transfers it to the metal gate material itself. By selecting metal gate materials with appropriate work functions, the Vt control capability is achieved directly through the gate electrode, eliminating the need for additional ground plane and back gate structures, thereby reducing device structure complexity while maintaining Vt modulation capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9406679B2Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate
Publication Date: 2016.08.02 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9406679B2 patent drawing
  • US9406679B2 patent drawing
  • US9406679B2 patent drawing

AI summary

A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.