Dual-Layer Gate Insulating Layer for Thin Film Transistors
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Solution Overview
Problem
The existing methods for fabricating thin film transistor array substrates face challenges with inorganic gate insulating layers, which complicate the fabrication process and increase production costs, while organic layers result in low dielectric constant issues leading to parasitic capacitance problems that affect display quality.
Innovation Solution
A dual-layer gate insulating layer is formed using a sol-gel type first layer and an inorganic or organic polymer second layer, with at least one layer being an organic/inorganic hybrid material, enhancing the dielectric constant and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an inorganic gate insulating layer is formed using PECVD process, then the dielectric constant is improved, but the fabrication process complexity increases and production cost increases
Solution Approach 1:
The gate insulating layer is divided into two separate layers: a first inorganic gate insulating layer formed by PECVD process providing high dielectric constant, and a second organic gate insulating layer formed by spin coating process providing uniform thickness. This segmentation allows each layer to fulfill its specific function independently, resolving the contradiction between achieving high dielectric constant and maintaining simple fabrication process
Solution Approach 2:
The gate insulating layer uses a composite structure combining inorganic material (silicon nitride or silicon oxide) for high dielectric constant properties and organic material for uniform thickness and simple formation process. This composite approach leverages the advantages of both material types to simultaneously improve reliability while managing fabrication complexity
2Reliability
If an inorganic gate insulating layer is formed using PECVD process, then the dielectric constant is improved, but the production cost increases
Solution Approach 1:
The gate insulating layer is divided into two separate layers: a first inorganic gate insulating layer formed by PECVD process providing high dielectric constant, and a second organic gate insulating layer formed by spin coating process providing uniform thickness. This segmentation allows each layer to fulfill its specific function independently, resolving the contradiction between achieving high dielectric constant and maintaining simple fabrication process
Solution Approach 2:
The gate insulating layer uses a composite structure combining inorganic material (silicon nitride or silicon oxide) for high dielectric constant properties and organic material for uniform thickness and simple formation process. This composite approach leverages the advantages of both material types to simultaneously improve reliability while managing fabrication complexity
3Device complexity
If a single deposition process is used for gate insulating layer, then the fabrication process is simplified, but the thickness uniformity deteriorates
Solution Approach 1:
The gate insulating layer is divided into two separate layers: a first inorganic gate insulating layer formed by PECVD process providing high dielectric constant, and a second organic gate insulating layer formed by spin coating process providing uniform thickness. This segmentation allows each layer to fulfill its specific function independently, resolving the contradiction between achieving high dielectric constant and maintaining simple fabrication process
Solution Approach 2:
Different regions of the gate insulating layer are assigned different materials with different properties: the first inorganic layer provides high dielectric constant while the second organic layer provides uniform thickness. This local differentiation of material properties allows each layer to optimize for its specific function, resolving the contradiction between process simplicity and thickness uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the storage capacitance, reduces voltage drop, and improves display quality by increasing the dielectric constant of the gate insulating layer, while simplifying the fabrication process and reducing costs.
Implementation Method 1
forming first and second gate insulating layers between the gate electrode and the semiconductor layer, wherein the first gate insulating layer is formed of a material different from the second gate insulating layer and at least one of the first and second gate insulating layers includes a sol-compound
Implementation Method 2
enhancing the dielectric constant and simplifying the fabrication process
Data Source
AI summary
A method for fabricating a thin film transistor (TFT) on a substrate includes forming a gate electrode; forming a semiconductor layer being insulated from the gate electrode and partially overlapped with the gate electrode; sequentially forming first and second gate insulating layers between the gate electrode and the semiconductor layer, wherein the first gate insulating layer is formed of a material different from the second gate insulating layer and at least one of the first and second gate insulating layers includes a sol-compound; and forming source and drain electrodes at both sides of the semiconductor layer.