JFET Pinch-Off Voltage Control via Lateral Well Width
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Solution Overview
Problem
It is challenging to precisely determine and achieve a desired pinch-off voltage in semiconductor junction-field-effect-transistor (JFET) devices due to variations in well-region depth and complexity in fabrication processes, particularly in lateral-type JFET devices.
Innovation Solution
The design and fabrication of a JFET device with a substrate and well regions of specific impurity types, including a patterned conductive layer with source, gate, and drain terminals, where the pinch-off voltage is controlled by varying the width of well regions and diffused regions, allowing for precise determination and adjustment of the pinch-off voltage through the lithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the depth of the well region is controlled to achieve a desired pinch-off voltage, then the pinch-off voltage can be adjusted, but it is difficult to precisely determine and control the depth during fabrication
Solution Approach 1:
The patent transitions from controlling well region depth (vertical dimension) to controlling well region width (horizontal dimension). The pinch-off voltage is now determined by the width of the well region formed by ion implantation, which can be precisely controlled through lateral mask dimensions rather than difficult-to-measure depth parameters. This dimensional shift resolves the measurement and control precision issues.
2Ease of manufacture
If a lateral-type JFET device is used to simplify fabrication alignment, then the fabrication process is simplified, but the pinch-off voltage becomes susceptible to fabrication process variations
Solution Approach 1:
The patent changes the controlling parameter from well region depth to well region width. By controlling the lateral dimensions of the ion implantation mask rather than the depth, the pinch-off voltage becomes more precisely controllable while maintaining the fabrication simplicity of lateral-type devices. The width parameter is more easily controlled through standard lithography processes.
3Adaptability or versatility
If the well region depth is varied to achieve different pinch-off voltages, then devices with different characteristics can be created, but it is difficult to design devices with desirable pinch-off voltages
Solution Approach 1:
The patent enables easy creation of devices with different pinch-off voltages by varying the lateral width of the well region through ion implantation mask design, rather than varying depth. This provides both adaptability for different device characteristics and precise control over the pinch-off voltage specification through well-established lateral dimension control in semiconductor fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of JFET devices with a predetermined pinch-off voltage, facilitating the fabrication of devices with desired characteristics and enabling the formation of multiple JFET devices with different pinch-off voltages on a single wafer, suitable for system-on-a-chip (SOC) devices.
Implementation Method 1
by controlling the voltages applied to its gate and drain terminals, depletion regions and currents may be induced
Implementation Method 2
forming a fourth well region of the first-type impurity between the second well region and the third well region
Data Source
AI summary
A method of manufacturing a junction-field-effect-transistor (JFET) device, the method includes the steps of providing a substrate of a first-type impurity; forming a first well region of a second-type impurity in the substrate; forming a second well region and a third well region of the first-type impurity separated from each other in the first well region; forming a fourth well region of the first-type impurity between the second well region and the third well region; forming a first diffused region of the second-type impurity between the second well region and the fourth well region; forming a second diffused region of the second-type impurity between the third well region and the fourth well region; forming a pair of first doped regions of the second-type impurity in the first well region, and a pair of second doped regions of the first-type impurity in the second well region and the third well region respectively; forming a third doped region of the second-type impurity in the first well region between the second well region and the third well region over the fourth well region; and forming a patterned conductive layer including a pair of drain terminals on the pair of first doped regions, a pair of gate terminals on the pair of second doped regions, and a source terminal on the third doped region.