Continuous Cell Pillar for 3D Memory Current Flow
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Solution Overview
Problem
Prior art 3D memory devices suffer from reduced current flow due to pinch-points caused by separate photolithography steps forming drain-side select gates over memory cells, leading to structural offsets and increased process steps and costs.
Innovation Solution
A continuous cell pillar is formed from the source-side select gate to the drain-side select gate, eliminating polysilicon-to-polysilicon interfaces and reducing the number of chemical-mechanical planarization steps, thereby improving current flow and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate photolithography steps are used to form drain-side select gates over memory cells, then the select gate structure can be formed, but pinch-points are created that reduce current flow
Solution Approach 1:
The patent merges the formation of the cell pillar and drain-side select gate into a single integrated structure formed by one photolithography step. The cell pillar is formed to extend through the memory cell region, and the drain-side select gate is formed directly over the cell pillar, eliminating the need for separate photolithography steps and the resulting structural offsets that cause pinch-points.
2Ease of manufacture
If separate photolithography steps are used to form select gates, then the gate structure can be created, but the number of process steps increases
Solution Approach 1:
The patent combines multiple fabrication steps into fewer operations. Specifically, the cell pillar and drain-side select gate are formed in a single photolithography step rather than separate steps, and chemical-mechanical planarization is reduced from multiple steps to a single step, thereby simplifying the overall manufacturing process.
3Reliability
If continuous cell pillar is formed from source-side select gate to drain-side select gate, then polysilicon-to-polysilicon interfaces are eliminated, but the fabrication process must be redesigned
Solution Approach 1:
The patent forms the cell pillar and drain-side select gate as an integrated structure in a single photolithography step, creating a continuous polysilicon structure without interfaces. This merging approach eliminates the polysilicon-to-polysilicon interfaces that would otherwise disrupt current flow, while the fabrication process is simplified rather than complicated.
4Manufacturing precision
If multiple chemical-mechanical planarization steps are used, then surface flatness can be achieved, but process complexity and costs increase
Solution Approach 1:
The patent reduces the number of chemical-mechanical planarization steps from multiple steps to a single step by integrating the cell pillar and select gate formation. This single planarization step is sufficient to achieve the required surface flatness for subsequent processing, thereby reducing process complexity and costs while maintaining manufacturing precision.
Data Source
AI summary
Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.