Gate-All-Around Semiconductor Threshold Voltage Adjustment

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Solution Overview

Problem

Conventional horizontal gate-all-around (GAA) transistors face challenges in controlling threshold voltage due to smaller depletion regions and mobility degradation from heavy doping, making it difficult to adjust threshold voltage effectively.

Innovation Solution

The method involves forming semiconductor structures with alternating layers of silicon and silicon germanium, using a dummy gate stack and etching processes to create voids and adjust the electrical length of channels, allowing for flexible threshold voltage adjustment by controlling the lateral dimensions of high-k metal gates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If heavy doping is used to adjust threshold voltage, then threshold voltage control is improved, but mobility degradation occurs

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidmobility degradation
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent changes the physical parameters of the gate structure by forming high-k metal gates with controlled lateral dimensions. By adjusting the gate width and length parameters during fabrication, the threshold voltage is tuned without relying on heavy doping, thus avoiding mobility degradation while achieving precise threshold voltage control.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures including high-k dielectric materials (such as hafnium oxide) combined with metal gate materials. This composite gate structure provides both the electrical field control needed for threshold voltage adjustment and the physical geometry control needed to avoid doping-related mobility degradation.

Inventive Principle:
Principle #40Composite materials

2Length of moving object

If conventional HGAA device scaling is pursued, then gate control is improved, but threshold voltage control becomes difficult

Engineering Contradiction:
Improvegate-channel couplingVSAvoidthreshold voltage control
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent introduces lateral dimension control of the high-k metal gate as an additional degree of freedom for threshold voltage adjustment. Instead of relying solely on vertical gate-channel coupling, the lateral dimensions (width and length) of the gate are precisely controlled during fabrication to provide an extra dimension for tuning threshold voltage in scaled devices.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If dummy polysilicon is used for threshold voltage adjustment, then threshold voltage control is improved, but cell size increases

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidcell size
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent extracts and eliminates the dummy polysilicon element from the device structure. Instead of adding extra polysilicon regions for threshold voltage adjustment, the invention uses the active high-k metal gate itself with controlled lateral dimensions to provide the threshold voltage tuning function, thereby removing the need for additional space-consuming dummy structures.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11043423B2Threshold voltage adjustment for a gate-all-around semiconductor structure
Publication Date: 2021.06.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11043423B2 patent drawing
  • US11043423B2 patent drawing
  • US11043423B2 patent drawing

AI summary

A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.