Cylindrical Storage Node Capacitor for DRAM Fabrication
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Solution Overview
Problem
Current methods for fabricating high-performance capacitors in DRAM devices face challenges such as limited etch depth, alignment issues, and risk of electrical shorts, particularly in forming high aspect ratio cell capacitors and multi-stack structures, which affect capacitance and manufacturing complexity.
Innovation Solution
The formation of a high capacitance embedded metal interconnect capacitor structure using a multi-stack approach with a conductive plate layer surrounding a cylinder-shaped storage node electrode, eliminating the need for etch stop layers and reducing the risk of electrical shorts by sandwiching the conductive plate layer between dielectric layers, thereby protecting the capacitor dielectric layer and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a cylindrical capacitor structure is fabricated with high aspect ratio contact etch, then the capacitance is increased, but the etch depth is limited and manufacturing becomes difficult
Solution Approach 1:
The capacitor structure is divided into multiple segments or sections along the vertical axis. Instead of forming one continuous high-aspect-ratio cylindrical electrode, the structure is segmented into multiple lower-aspect-ratio sections that can be fabricated separately and then connected, bypassing the etch depth limitation while maintaining high capacitance through the cumulative effect of multiple segments
Solution Approach 2:
The invention transitions from a purely vertical high-aspect-ratio cylindrical structure to a multi-dimensional structure that incorporates lateral extensions or stacked configurations. By adding horizontal dimensions through lateral electrode extensions or stacking multiple capacitor units, the design achieves high capacitance without requiring excessive etch depth
2Quantity of substance
If multi-stack capacitor structures are formed to increase capacitance, then the capacitance is improved, but alignment precision is compromised and electrical shorts occur
Solution Approach 1:
Alignment features, registration marks, or guiding structures are formed in advance during earlier fabrication steps. These preliminary structures serve as templates or references for subsequent stacking operations, ensuring precise alignment of multiple capacitor stacks before the actual stacking process begins, thereby maintaining manufacturing precision while achieving high capacitance
Solution Approach 2:
An intermediary layer or structure is introduced between the stacked capacitor elements to facilitate precise alignment and prevent electrical shorts. This intermediary component acts as a mediator that provides both mechanical positioning guidance and electrical isolation, enabling multi-stack configurations without compromising alignment precision or creating short circuits
3Reliability
If control liner layers are etched to recess the outer electrode, then electrical shorts are prevented, but the fabrication process becomes more complex
Solution Approach 1:
The problematic control liner layer that requires complex etching operations is completely removed or extracted from the fabrication process. Instead of using this intermediate layer to prevent electrical shorts, the design employs alternative structures such as inherent dielectric barriers, recessed electrode configurations achieved through different etching strategies, or spatial separation techniques that eliminate the need for control liner layers entirely, thereby reducing fabrication complexity while maintaining reliability
Data Source
AI summary
A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer.