3D Memory Charge Storage Segmentation for Leakage Control

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Solution Overview

Problem

Conventional semiconductor memory devices with three-dimensionally arranged memory cells face challenges in enhancing data retention characteristics due to electrical charge leakage between adjacent charge storage regions, leading to erroneous writing and data loss.

Innovation Solution

A nonvolatile semiconductor memory device is designed with a laminated structure featuring charge storage regions mainly containing carbon, electrically separated by insulating regions, which are formed on the inner walls of through holes and extend along specific directions, preventing charge transfer between memory cell transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If charge storage layers are provided around columnar semiconductors in three-dimensionally arranged memory cells, then data storage capacity is improved, but electrical charge leakage between adjacent charge storage regions occurs causing data retention deterioration

Engineering Contradiction:
Improvedata storage capacityVSAvoiddata retention characteristics
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The charge storage layer is segmented into discrete regions by introducing insulating regions between adjacent charge storage areas. These insulating regions act as barriers that divide the continuous charge storage space into isolated segments, preventing electrical charge leakage between neighboring memory cells while maintaining high storage capacity through three-dimensional arrangement.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Insulating regions are introduced as intermediary structures between adjacent charge storage regions. These intermediary insulating regions serve as electrical barriers that prevent direct charge transfer between neighboring charge storage areas, thereby improving data retention characteristics without compromising the three-dimensional memory cell architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If three-dimensional memory cell arrangement is implemented to enhance integration density, then device compactness is improved, but charge leakage between adjacent cells increases

Engineering Contradiction:
Improveintegration densityVSAvoidcharge leakage between cells
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The continuous charge storage layer in three-dimensionally arranged memory cells is divided into discrete, isolated regions by inserting insulating regions between adjacent charge storage areas. This segmentation maintains the high integration density of three-dimensional architecture while preventing harmful charge leakage between neighboring cells through the insulating barriers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the memory device are assigned different functional properties: charge storage regions are designed for high-density charge accumulation, while insulating regions are specifically designed with high electrical resistance to prevent charge leakage. This local differentiation of material properties allows simultaneous achievement of high integration density and low charge leakage.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8809931B2Nonvolatile semiconductor memory device
Publication Date: 2014.08.19 KIOXIA CORP
  • US8809931B2 patent drawing
  • US8809931B2 patent drawing
  • US8809931B2 patent drawing

AI summary

According to one embodiment, there is provided a nonvolatile semiconductor memory device including a substrate, a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate, a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction, an intermediate layer formed on a surface of the second insulating layer, a third insulating layer formed on a surface of the intermediate layer, and a pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction.