Nonvolatile Memory Floating Gate Sidewall Integration
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Solution Overview
Problem
In highly integrated semiconductor devices, the narrow width of floating gates and decreasing gap between them lead to increased leakage current and difficulty in securing a desired threshold voltage during program operations, as well as insufficient space for forming control gates in nonvolatile memory devices.
Innovation Solution
The nonvolatile memory device design includes a substrate with active regions defined by an isolation layer, where floating gates are formed with a tunnel dielectric layer in between, and control gates are placed over an intergate dielectric layer, allowing for a sufficient channel width and space between floating gates without increasing the floating gate width, by forming first sidewalls of active regions to extend upward and supporting floating gates with isolation layers in narrower gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of floating gates is decreased to achieve higher integration, then the integration density is improved, but leakage current increases and threshold voltage control becomes difficult
Solution Approach 1:
The patent transitions from a planar floating gate structure to a three-dimensional structure where the floating gate adjoins the sidewalls of the active region. This vertical arrangement allows the floating gate to extend along the sidewall surface, effectively increasing the functional area without increasing the planar footprint, thus maintaining high integration while improving electrical characteristics
Solution Approach 2:
The patent employs a composite structure combining the floating gate, tunnel dielectric layer, and active region sidewalls. This composite arrangement creates a multi-functional structure where the floating gate serves both as a storage element and as a component that defines the channel region, enabling better control of leakage current and threshold voltage
2Productivity
If the gap between floating gates is decreased to increase integration, then the device density is improved, but sufficient space for forming control gates becomes insufficient
Solution Approach 1:
The patent utilizes the vertical dimension by having the floating gate adjoin the sidewalls of the active region. This allows the control gate to be formed over the intergate dielectric layer in the space between adjacent floating gates, while the floating gates themselves extend vertically along the sidewalls. This three-dimensional arrangement provides sufficient space for control gate formation even when the planar gap between floating gates is small
Solution Approach 2:
The patent segments the floating gate structure into portions that adjoin the sidewalls of the active region. This segmentation allows the floating gate to be positioned in a way that creates adequate spacing for the intergate dielectric layer and control gate formation, while still maintaining close proximity between adjacent memory cells for high integration
3Reliability
If the width of floating gates is increased to maintain threshold voltage, then the channel width is reduced, but integration density decreases
Solution Approach 1:
The patent resolves this contradiction by moving the floating gate structure into the vertical dimension, where it adjoins the sidewalls of the active region. This allows the floating gate to have sufficient effective width for threshold voltage control while the planar footprint remains small, maintaining high integration density
Solution Approach 2:
The patent applies local quality by having the floating gate adjoin specifically the sidewalls of the active region rather than spanning the entire width. This localized arrangement provides the necessary electrical characteristics for threshold voltage control in the critical region while minimizing the overall device area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration secures the channel width of memory cells and provides sufficient space for forming intergate dielectric and control gates, reducing leakage current and facilitating program operations by optimizing the arrangement of floating and control gates.
Implementation Method 1
a program operation for storing charges in the floating gates 13 or an erase operation for removing the charges stored in the floating gates 13 is performed according to a voltage applied to the control gates 15
Data Source
AI summary
A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.