Bi-phase Mark Code Decoder Using SPI Oversampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing wireless charging systems face challenges in decoding bi-phase mark coded (BMC) data due to high cost, complexity, and stringent latency requirements when using dedicated hardware, and firmware-based solutions struggle with design flexibility and processing constraints.
Innovation Solution
The use of firmware and existing hardware blocks, such as the serial peripheral interface (SPI) module, to sample and decode BMC-encoded signals, allowing for oversampling and post-processing to compensate for clock jitter and frequency deviations, thereby reducing processing bandwidth and design constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated hardware is used to decode BMC signal, then decoding accuracy and reliability are improved, but cost and device complexity increase
Solution Approach 1:
The patent uses a software-based BMC decoder that replicates the functionality of dedicated hardware through firmware implementation. The SPI module samples the BMC signal and the processor executes decoding algorithms, creating a software copy of hardware decoding functionality. This approach maintains decoding accuracy while eliminating the need for specialized hardware circuits.
Solution Approach 2:
The patent employs a general-purpose processor with SPI module that can perform multiple functions including BMC signal sampling, data decoding, and communication protocols. This universal processor replaces dedicated hardware decoders, reducing device complexity while maintaining decoding capability through software implementation.
2Ease of manufacture
If firmware-based decoding is used, then cost and design flexibility are improved, but processing bandwidth consumption increases
Solution Approach 1:
The patent segments the decoding process into distinct phases: the SPI module handles signal sampling and data acquisition, while the processor handles the actual BMC decoding algorithms. This segmentation allows the processor to focus only on the computationally intensive decoding portion, reducing overall bandwidth consumption compared to a monolithic firmware approach.
Solution Approach 2:
The SPI module performs preliminary actions by sampling the BMC signal and preparing the data before it reaches the processor. This preliminary data preparation reduces the processing burden on the main processor, as the raw signal processing is already completed by the dedicated SPI hardware interface.
3Adaptability or versatility
If firmware decoding is used, then design flexibility is improved, but latency increases due to processing constraints
Solution Approach 1:
The patent implements a dynamic decoding architecture where the processor can be configured to handle BMC decoding with adjustable processing parameters. The system dynamically allocates processing resources and adjusts decoding timing based on signal characteristics, maintaining low latency while preserving design flexibility through software configuration rather than fixed hardware timing.
Data Source
AI summary
Disclosed are techniques for using firmware and hardware blocks of a device to decode signals encoded by signal edge positioning within a data bit width, such as bi-phase mark space coding (BMC) used for encoding in-band communication of wireless charging systems. The first device may use general purpose I/O (GPIO) interrupts to detect the start of a packet. The firmware may synchronize and configure the clock of a serial peripheral interface (SPI) to oversample the signals. The SPI may store the sampled data into a buffer, freeing the firmware from having to expend processing cycles to detect the transitions of the data in real-time. The firmware may read the buffered samples to decode the packet data in a post-processing stage. The firmware may detect the end of the packet by polling and GPIO interrupts or based on the samples read from the buffer to stop the clock of the SPI.