Bond Pad Layout With Floating Sections for Lower Parasitic Capacitance

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Solution Overview

Problem

Integrated circuit bonding pads face challenges with parasitic capacitance, which degrades signal quality, especially in high-speed applications, due to the large area of conductive layers required for bond wire support and alignment, leading to mechanical stress and signal degradation.

Innovation Solution

Incorporating intermediate conductive layers that are sectioned into connected and floating sections between the top bonding pad layer and under-pad circuits, reducing parasitic capacitance without decreasing the bonding area, and maintaining mechanical stress tolerance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the conductive layer area is increased to support bond wire alignment and bonding, then the bonding area is improved, but the parasitic capacitance increases causing signal degradation

Engineering Contradiction:
Improvebonding areaVSAvoidparasitic capacitance
Core Design Contradiction:
Area of moving objectVSObject-generated harmful factors

Solution Approach 1:

The intermediate conductive layer is divided into multiple separate conductive sections instead of being a continuous layer. Each conductive section is electrically isolated from others by dielectric material, which reduces the total parasitic capacitance while still providing sufficient bonding area for wire attachment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the bonding pad structure are assigned different functions: the top conductive layer provides bonding surface area, the intermediate layer provides mechanical stress relief through its segmented structure, and the bottom conductive layer connects to the circuit. This localized functional assignment optimizes each region for its specific purpose while minimizing overall parasitic capacitance.

Inventive Principle:
Principle #3Local quality

2Strength

If intermediate conductive layers are added to reduce mechanical stress propagation, then the mechanical stress tolerance is improved, but the device complexity increases

Engineering Contradiction:
Improvemechanical stress toleranceVSAvoidstructure complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The intermediate conductive layer is segmented into multiple isolated sections rather than being continuous. This segmentation provides mechanical stress relief by allowing the structure to flex independently in different regions, while the sections remain electrically isolated to minimize capacitance. The segmented design achieves stress tolerance without requiring additional complex stress-management components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The intermediate conductive layer serves multiple functions simultaneously: it provides mechanical stress relief, maintains electrical isolation between different conductive layers, and offers a bonding surface for wire attachment. This multi-functionality reduces the need for separate dedicated stress-management structures, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively decreases parasitic capacitance, improving signal quality and allowing for larger bonding surfaces while maintaining mechanical stress management, thus enhancing the performance of bonding pads in high-speed applications.

Implementation Method 1

parasitic capacitance Cparasitic experienced by signals transmitted by the bond wire 102 is a capacitance C1 between the bottom-most conductive layer 108b of the bonding arrangement 100 and the under-pad conductive layers 116

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS11887949B2Bond pad layout including floating conductive sections
Publication Date: 2024.01.30 MACRONIX INTERNATIONAL CO LTD
  • US11887949B2 patent drawing
  • US11887949B2 patent drawing
  • US11887949B2 patent drawing

AI summary

Disclosed is a semiconductor device that has a first layer including conductive material, a bond wire coupled to an upper surface of the first layer, and a second layer including conductive material underneath the first layer. One or more interconnects couple the second layer to the first layer. In an example, the second layer has a plurality of discontinuous sections that includes (i) a connected section coupled to the one or more interconnects and (ii) one or more floating sections that are at least in part surrounded by the connected section, where the one or more floating sections are electrically floating and isolated from the connected section. The semiconductor device also includes an under-pad circuit on a substrate underneath the second layer, the under-pad circuit to transmit signals to one or more components external to the semiconductor device though the first layer.