Bond Pad Segmentation for Low Temperature Flip Chip
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for 3D integrated semiconductor devices face challenges with dishing of bond pad surfaces during chemical-mechanical polishing (CMP), leading to voids in copper interconnects between joined semiconductor devices, which affects the structural integrity and electrical interconnections.
Innovation Solution
The method involves forming bond pads with different or rotated configurations of metal segments on semiconductor devices, allowing for staggered or angled arrangements, and bonding them through copper-to-copper contacts using a copper damascene process and low temperature inorganic dielectric layers, minimizing dishing and voids during CMP and subsequent bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical-mechanical polishing (CMP) is used to planarize bond pad surfaces, then surface flatness is improved, but dishing of bond pads occurs leading to voids in copper interconnects
Solution Approach 1:
The bond pad surface is segmented into multiple metal segments arranged in different configurations on opposing devices. This segmentation allows the CMP process to planarize each segment independently, reducing the dishing effect that occurs on large continuous surfaces while maintaining overall surface flatness for proper alignment and bonding.
Solution Approach 2:
Metal segments on opposing bond pads are configured asymmetrically or rotated relative to each other. This asymmetric arrangement ensures that the segments do not align perfectly, distributing the contact points during bonding and preventing the formation of continuous voids that would occur with symmetric, aligned configurations.
2Reliability
If metal segments are arranged in different or rotated configurations on opposing bond pads, then dishing and voids are reduced, but manufacturing complexity increases
Solution Approach 1:
The bond pad is divided into multiple metal segments that can be arranged in various configurations. This segmentation approach maintains manufacturing simplicity by using standard fabrication processes while achieving the reliability benefits of reduced dishing and void formation through the segmented structure.
Solution Approach 2:
The configuration parameters of metal segments (such as orientation, spacing, and arrangement pattern) are optimized to balance manufacturing complexity with performance. By carefully selecting segment configurations that can be achieved with existing fabrication capabilities, the patent achieves reduced dishing and voids without excessive manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces dishing and voids, enhancing the reliability of interconnects and allowing for improved bonding with multiple contact points, thus improving the structural and electrical integrity of 3D integrated devices.
Implementation Method 1
copper is deposited in the vias by plating or chemical vapor deposition (CVD) of the copper
Implementation Method 2
copper is deposited in the vias by plating or chemical vapor deposition (CVD) of the copper
Implementation Method 3
the surface of the copper and dielectric layer is planarized by chemical-mechanical polishing (CMP)
Implementation Method 4
dielectric layers, for example low temperature inorganic dielectrics such as silicon dioxide (SiO2), silicon nitride (Si3N4), and/or silicon carbide (SiC) are formed on the wafer
Implementation Method 5
dielectric layers, for example low temperature inorganic dielectrics such as silicon dioxide (SiO2), silicon nitride (Si3N4), and/or silicon carbide (SiC) are formed on the wafer and etched to form vias
Implementation Method 6
after annealing, interconnects between the devices are formed through copper-to-copper bonds in the bond pads
Implementation Method 7
The preprocessed wafers are aligned and bonded together at or near room temperature using chemical or plasma activated fusion bonding processes compatible with back-end-of-the-line (BEOL) wafers. As the surfaces of the dielectric layers are physically bonded together
Data Source
AI summary
Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.