Bond Pad Stress Buffer Structure for SoIC CTE Mismatch
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Solution Overview
Problem
The challenge of coefficient-of-thermal-expansion (CTE) mismatches between metal pads and surrounding dielectric layers weakens bonding strength in system-on-integrate-chip (SoIC) structures, affecting circuit performance and reliability.
Innovation Solution
A bonding structure with a stress buffer zone (stress release zone) is introduced, featuring recesses encircling bond pads to accommodate thermal expansion, formed through selective wet etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If metal pads are bonded to dielectric layers in SoIC structures, then bonding strength is required for structural integrity, but CTE mismatch between metal pads and dielectric layers causes warpage and weakens bonding strength
Solution Approach 1:
The patent segments the metal pad structure by introducing recesses or voids within the metal pad material. This segmentation creates a stress buffer zone that divides the continuous metal pad into regions separated by voids, allowing differential thermal expansion without generating excessive stress that would compromise bonding strength or cause warpage.
Solution Approach 2:
The patent introduces a porous or void-containing structure within the metal pad, creating a stress buffer zone with lower density and different mechanical properties. This porous region accommodates thermal expansion by providing space for material displacement, reducing the harmful effects of CTE mismatch while maintaining overall bonding integrity.
2Ease of manufacture
If standard metal pad bonding is used without stress accommodation features, then manufacturing process is simple, but thermal expansion causes warpage and reduces bonding strength
Solution Approach 1:
The patent applies preliminary action by forming recesses or voids within the metal pad structure before the bonding process. This pre-creation of stress buffer zones ensures that when thermal expansion occurs during bonding or operation, the accommodative structure is already in place, preventing warpage and maintaining bonding strength without complicating the overall manufacturing flow.
3Reliability
If recesses are added to metal pads to accommodate thermal expansion, then warpage is reduced and bonding strength is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the physical structure of the metal pad through recesses or voids, changing its mechanical and thermal parameters. This structural modification allows the metal pad to accommodate thermal expansion more effectively, improving bonding reliability while the complexity increase is managed through standardized fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress buffer zone reduces warpage and enhances bonding strength, improving the reliability and performance of SoIC structures by accommodating thermal expansion.
Implementation Method 1
coefficients-of-thermal-expansion (CTEs) mismatches between metal pads and surrounding dielectric layers may weaken bonding strength
Implementation Method 2
selectively etching the first metal pad to form recesses at an edge portion of the first metal pad
Data Source
AI summary
A method includes depositing a first dielectric layer on a first substrate of a first device die, etching the first dielectric layer to form a trench, depositing a metallic material in the trench and on a top surface of the first dielectric layer, and performing a chemical mechanical polish (CMP) process to remove a portion of the metallic material from the top surface of the first dielectric layer to form a first metal pad. After the performing of the CMP process, the method selectively etches the first metal pad to form recesses at an edge portion of the first metal pad, deposits a second dielectric layer on a second substrate of a second device die, forms a second metal pad in the second dielectric layer, and bonds the second device die to the first device die.