Bonded 3D Memory Chip Layout for High-Density Scaling
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Solution Overview
Problem
The integration of control circuits and memory arrays in 3D memory structures leads to increased area occupation and process incompatibility issues, limiting the manufacturing of small-sized high-density storage devices.
Innovation Solution
The memory array chip and control circuit chip are bonded separately, with memory cells and circuit structures facing each other and connected through a bonding structure, allowing for decoupled manufacturing processes and improved storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the control circuit and memory array are integrated on the same chip surface and arranged in parallel, then the manufacturing process is simplified, but the area occupied by the control circuit increases proportionally with stacking height, which is not conducive to manufacturing small-sized high-density storage devices
Solution Approach 1:
The patent transitions from a 2D parallel arrangement to a 3D stacked architecture where the memory array is vertically stacked above the control circuit. This dimensional change allows the memory array to occupy the Z-direction (vertical stacking) while the control circuit remains on the substrate plane, thereby reducing the 2D area occupied by the control circuit and enabling higher storage density in a smaller footprint.
2Volume of moving object
If the control circuit is manufactured first and then the memory array is stacked above it, then the 2-dimensional dimension of the storage device is reduced, but the high-temperature manufacturing process of the memory array affects the performance of the control circuit
Solution Approach 1:
The patent divides the storage device into two separate chips: a control circuit chip and a memory array chip. This segmentation allows each chip to be manufactured independently using optimized processes for their respective functions, avoiding the process incompatibility issue where high-temperature memory array manufacturing would damage the control circuit. The chips are then bonded together through a bonding structure.
Solution Approach 2:
The patent introduces a bonding structure as an intermediary element that connects the control circuit chip and the memory array chip. This bonding structure serves as a mediator that enables electrical and physical connection between the two separately manufactured chips, allowing the memory array to be stacked above the control circuit without direct thermal exposure during manufacturing.
3Quantity of substance
If the memory array stacking height is increased to achieve higher storage density, then the storage capacity is improved, but the proportion of area occupied by the control circuit on the substrate increases
Solution Approach 1:
The patent utilizes vertical stacking in the Z-direction to increase storage capacity while keeping the control circuit area on the substrate constant. By stacking multiple memory array layers above the control circuit, the storage density increases proportionally with the number of stacked layers, while the control circuit occupies only the substrate plane area, thus reducing its proportional area as storage capacity increases.
Data Source
AI summary
The present disclosure relates to memories, electronic devices, and memory manufacturing methods. One example memory includes a memory array chip and a control circuit chip. The memory array chip includes a first substrate and a plurality of memory cells formed on the first substrate, and each memory cell includes a transistor and at least one capacitor electrically connected to the transistor. The control circuit chip includes a second substrate and a circuit structure formed on the second substrate, and the circuit structure is configured to control reading/writing of the plurality of memory cells. The plurality of memory cells and the circuit structure face each other and are electrically connected to each other through a bonding structure formed between the circuit structure and the plurality of memory cells.