Bonded NAND Memory Chip Layout for Higher Bandwidth
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Solution Overview
Problem
Current NAND-type flash memory systems face challenges in increasing communication bandwidth and storage capacity while minimizing parasitic components and costs, particularly due to the separation of memory cell arrays and peripheral circuits across different chips.
Innovation Solution
The memory system integrates a memory controller and input/output module within a CMOS chip, reducing parasitic components and allowing for a bonded structure that increases the area occupied by memory cell arrays, and optionally uses a stacked configuration of core chips with a shared input/output module and controller chip to enhance communication speed and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory cell arrays and peripheral circuits are separated across different chips, then device complexity is reduced and manufacturing is easier, but parasitic components increase and communication bandwidth is limited
Solution Approach 1:
The patent combines peripheral circuits and memory cell arrays onto the same chip to reduce parasitic components and improve communication bandwidth, while using a stacked configuration with multiple chips bonded together to achieve the desired integration level without excessive complexity in individual chips
2Object-generated harmful factors
If memory cell arrays and peripheral circuits are integrated on the same chip, then parasitic components are reduced and communication bandwidth increases, but chip area requirements increase
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked configuration, bonding multiple chips vertically to increase integration density without requiring proportional increases in individual chip area
3Productivity
If communication bandwidth is increased through integration, then productivity improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the memory system into multiple functional chips bonded together in a stack, with each chip containing specific circuits, allowing high communication bandwidth within chips while maintaining manageable complexity through modular segmentation
Data Source
AI summary
According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.