3D Bonded Memory and CMOS Chips Reducing RC Time Constant
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Solution Overview
Problem
Semiconductor storage devices face challenges in reducing power consumption and increasing operation speed due to increased wire capacitance and resistance with smaller storage densities, leading to higher RC time constants and reduced cell current, especially in three-dimensionally stacked memory cells.
Innovation Solution
The semiconductor storage device employs a configuration where the memory cell array is divided into multiple portions, with the sense amplifier module shared across these portions, and the memory chip and CMOS chip are bonded together, allowing for overlapping of the sense amplifier region with the memory region, thereby reducing the RC time constant and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wire length is reduced to decrease RC time constant, then operation speed is improved, but chip area is reduced
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture where the memory chip and CMOS chip are bonded together in the vertical direction. This dimensional change allows the sense amplifier region to overlap with the memory region in the vertical axis, effectively reducing the horizontal wire length and RC time constant while maintaining or reducing the overall chip footprint area.
2Area of stationary object
If sense amplifier region overlaps with memory region, then chip area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor device into two separate functional chips: a memory chip containing the memory cell array and a CMOS chip containing the sense amplifier module. These segmented chips are manufactured separately using optimized processes for each function, then bonded together. This segmentation reduces the manufacturing complexity of integrating different functions in a single chip while enabling the sense amplifier region to overlap with the memory region in the vertical direction.
Solution Approach 2:
The patent introduces a bonding interface as an intermediary between the memory chip and CMOS chip. This bonding layer serves as a mediator that connects the two separately manufactured chips, allowing the sense amplifier region to be positioned in overlap with the memory region in the vertical direction. The bonding interface simplifies the manufacturing process by enabling separate fabrication of memory and CMOS components before final assembly.
3Use of energy by moving object
If wire capacitance and resistance are reduced, then power consumption is reduced, but cell current decreases
Solution Approach 1:
By stacking the CMOS chip containing the sense amplifier above or below the memory chip, the patent reduces the horizontal distance that bit lines must traverse. This vertical integration shortens the effective wire length, reducing both wire capacitance and resistance. The reduced RC time constant allows for lower operating voltage and current, decreasing power consumption while maintaining sufficient cell current for reliable read operations.
Data Source
AI summary
A semiconductor storage device includes a memory unit and a circuit unit bonded to the memory unit. The memory unit includes first and second memory cells, first and second bit lines respectively connected to the first and second memory cells, and first and second bonding metals respectively connected to the first and second bit lines. The circuit unit includes a sense amplifier unit including a first wire, a third bonding metal connected with the first wire and opposed to the first bonding metal, and a fourth bonding metal connected with the first wire and opposed to the second bonding metal.