Bonded Memory Array Layout With Segmented Decoder Routing
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Solution Overview
Problem
The existing semiconductor memory devices face issues with long routing lengths of main decoding signal lines, leading to varying delays and poor timing uniformity, exacerbated by limited width and spacing of these lines due to reduced device area and planar processes.
Innovation Solution
A memory structure with a bonded memory array chip and logic circuit chip, where row decoders and sub-wordline drivers are positioned above the memory array, allowing for a more efficient layout that reduces signal line lengths and decouples the need for peripheral placement, enabling shared decoding signals across multiple drivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the main decoding signal line is routed to connect the row decoder to all sub-wordline drivers across the entire section, then all memory array tiles can receive decoding signals, but the routing length becomes excessively long causing signal delay variations
Solution Approach 1:
The section is divided into multiple blocks, with each block containing a subset of memory array tiles. Each block has its own dedicated row decoder that generates main decoding signals locally. This segmentation eliminates the need for long routing lines spanning the entire section, as each block's row decoder only needs to connect to sub-wordline drivers within that block, significantly reducing routing length and improving timing uniformity.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. Row decoders are placed in different layers or levels above the memory array tiles, allowing signal lines to be routed vertically through interconnect structures. This dimensional change enables shorter signal paths by utilizing the vertical space, reducing the horizontal routing distance and improving timing uniformity across the memory section.
2Area of stationary object
If the device area is reduced and planar process is used, then device integration is improved, but the width and spacing of main decoding signal lines are limited increasing routing difficulty
Solution Approach 1:
By dividing the memory section into multiple smaller blocks, each with its own row decoder, the patent reduces the number of main decoding signal lines required in any given area. This segmentation decreases routing density and complexity within each block, making the routing process more manageable despite reduced overall device area and constraints of planar processing.
Solution Approach 2:
The three-dimensional stacked architecture allows main decoding signal lines to be routed in vertical interconnect layers rather than constrained to horizontal planes. This enables better utilization of available routing resources by using multiple routing layers in the vertical dimension, effectively increasing routing capacity without increasing the planar footprint, thus easing routing difficulty in compact devices.
3Productivity
If multiple row decoders are used for different memory array tiles, then decoding capacity is improved, but the quantity of main decoding signal lines increases
Solution Approach 1:
The patent segments the memory system into multiple independent blocks, where each block has its own row decoder serving only the memory array tiles within that block. This segmentation ensures that main decoding signal lines generated by one row decoder do not need to be routed to sub-wordline drivers in other blocks. Consequently, while the overall decoding capacity of the device increases due to multiple row decoders, the number of main decoding signal lines required per block remains manageable, as each decoder only serves its local block.
Data Source
AI summary
A memory includes a memory array chip and a logic circuit chip that are bonded. Each memory array tile corresponds to at least one row decoder, one sub-decoder, and at least one sub-wordline driver. Each row decoder provides a first quantity of main decoding signal lines. The sub-decoder provides a second quantity of sub-decoding signal lines. A product of a total quantity of main decoding signals from all row decoders corresponding to a single memory array tile and the second quantity is the same as a quantity of word lines of the single memory array tile. Each of the at least one sub-wordline driver is configured to drive a word line of the corresponding memory array tile based on the main decoding signal and the sub-decoding signal.