Digital Storage TRIZ Cases
- Memory Refresh Rate-Based Circuit Throttling for Thermal Control
A PMU compares requested and maximum refresh rates to throttle thermally coupled circuitry while limiting heat and power use.
- Memory Chip Strobe Delay Adjustment for PVT-Consistent Access
Chip-level strobe delay tuning stabilizes memory data access across PVT variation.
- Bonded Memory Array Layout With Segmented Decoder Routing
This case uses segmented row decoders and sub-wordline drivers in a bonded memory structure to reduce routing delay variation.
- MRAM Two-Terminal Selectors for Compact SOT-MRAM Stacking
This SOT-MRAM case vertically stacks the SOT conductor and bit line to improve density while reducing stacked conductive layers.
- Stacked DRAM with Twisted Bit-Line Connections for Lower Noise
Twisted bit-line connections in stacked DRAM reduce coupling noise and improve sense margin.
- Segmented Memory References for Column Loading and Read Margins
This case uses shared reference cells across memory segments to track loading effects, improve read margins, and reduce area.
- Cell-on-Periphery Memory Core Layout for Compact DRAM Circuits
This case places sense amplifiers at column edges and wordline drivers centrally beneath subarrays to improve DRAM design margin.
- Memory Array Connections Using FEOL-to-BEOL Vertical Routing
FEOL-to-BEOL vertical routing links sense amplifiers and word-line drivers to memory arrays, improving density and cell utilization.
- Memory Refresh Circuit with Dual-Window Row Hammer Detection
Dual-window row monitoring identifies aggressor rows for protective DRAM refresh.
- Weak-Cell-Aware DRAM Refresh Control for Row Hammer Mitigation
Weak-cell counting enables targeted DRAM refresh to reduce row hammer data loss.
- Semiconductor Word-Line Testing with Bit-Line Mismatch Cancellation
In semiconductor testing, bit-line equalization and a settling period expose voltage differences linked to word-line connection defects.
- Serial Read-Write Memory With Cleanup-Free Time Multiplexing
Selected-column cleanup is eliminated for faster, lower-power SRAM read/write cycles.
- Sense Amplifier Control for Adaptive Memory Read Timing
Feedback control ends sense-amplifier sensing when memory data is ready.
- On-Die Voltage Sensing and Digital Feedback for Memory Die Power Regulation
Voltage sensors within the memory die capture array conditions and send digital feedback to the PMIC for supply adjustment.
- Resistive Non-Volatile Memory Without Word-Line Overhead
This resistive memory case removes the gate electrode to reduce word-lines, circuit complexity, power use, and chip area.
- Memory Bitline Shielding with Dynamic Shield Voltage Control
Shield lines between DRAM bitlines receive voltage only when needed, reducing coupling errors and leakage during read operations.
- Multiple SRAM Cell Architectures for Cache Drive, Leakage, and Density
Varying n-type and p-type active-region widths tailor SRAM cells to cache levels, balancing drive current, standby leakage, and density.
- Sense Amplifier Asymmetry for Reduced Voltage Offset
Separated source connections and opposite Vsg polarities reduce offset, preserving sensing accuracy and reliability across PVT variations.
- PCRAM Memory Programming with R-Set and S-Reset Refresh Signals
This memory programming case uses targeted refresh signals to limit state drift while enabling blind programming in PCRAM.
- Cross-Point Memory Arrays for Bipolar Access with Simplified Peripherals
This case uses opposite-polarity biasing in cross-point arrays to switch memory cells while reducing peripheral circuitry complexity.
- Semiconductor Memory DM Impedance Control via Mode Registers
This case uses existing DQ-related mode registers to control DM impedance, avoiding extra driver logic and circuit errors during testing.