Memory Refresh Circuit with Dual-Window Row Hammer Detection
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Solution Overview
Problem
In volatile memory devices like DRAM, the row hammer effect causes data instability due to voltage distribution affecting adjacent rows, necessitating effective monitoring and refresh operations to prevent data loss.
Innovation Solution
A memory device with a refresh control circuit incorporating a row hammer managing circuit that includes multiple row address generators and a checker to identify aggressor rows, performing refresh operations on adjacent rows based on different monitoring lengths to mitigate the row hammer effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If intensive access to a certain row is performed to increase memory access speed, then access speed is improved, but data stability in adjacent rows deteriorates due to voltage distribution effects
Solution Approach 1:
The refresh control circuit performs preliminary detection of aggressor rows by monitoring access patterns over a first monitoring length, and before data corruption occurs in adjacent rows, proactively generates refresh commands to prevent the row hammer effect from compromising data stability
Solution Approach 2:
The system continuously monitors row access patterns and uses this feedback information to dynamically identify aggressor rows and adjust refresh operations, creating a closed-loop control mechanism that adapts to actual usage patterns and prevents data instability
2Measurement precision
If monitoring length is increased to improve detection accuracy of aggressor rows, then detection precision is improved, but time consumption for refresh operations increases
Solution Approach 1:
The monitoring process is divided into two distinct segments: a first monitoring length for rapid initial detection of potential aggressor rows, and a second monitoring length for verification and confirmation. This segmentation allows the system to balance detection accuracy with time efficiency by not always requiring the full second monitoring period
Solution Approach 2:
The system uses a partial monitoring approach where the first monitoring length provides sufficient detection capability for most cases, and the second monitoring length is only fully utilized when needed for confirmation, avoiding unnecessary time consumption while maintaining adequate detection precision
3Reliability
If all rows are monitored to ensure comprehensive data protection, then reliability is improved, but device complexity increases due to multiple monitoring circuits
Solution Approach 1:
The refresh control circuit performs multiple functions using a single integrated structure: it monitors row access patterns, detects aggressor rows, generates refresh commands, and manages the refresh timing. This multi-functionality eliminates the need for separate dedicated monitoring circuits for each row, reducing overall device complexity while maintaining comprehensive protection
Solution Approach 2:
The detection function and refresh control function are merged into a single refresh control circuit that handles both aggressor row identification and refresh command generation. This consolidation reduces the number of separate components and interconnections needed, simplifying the overall device architecture while ensuring all rows are protected
Data Source
AI summary
A memory device includes a plurality of memory cells and a refresh control circuit that generates a refresh row address and performs a refresh operation on memory cells of a row corresponding to the refresh row address. The refresh control circuit includes a row hammer managing circuit that includes a first row address generator that receives first input row addresses during a first monitoring length and determines a first candidate address among the first input row addresses based on a first reference address, a second row address generator that receives second input row addresses during a second monitoring length longer than the first monitoring length and determines a second candidate address among the second input row addresses based on a second reference address, and a row address checker that determines an aggressor row address based on the first candidate address and the second candidate address.