Stacked DRAM with Twisted Bit-Line Connections for Lower Noise
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Solution Overview
Problem
Existing DRAM architectures face significant noise issues due to large parasitic capacitance between bit lines, which adversely affect sense margin and limit storage density, particularly in 4F2 structures.
Innovation Solution
Implement a memory design with multiple layers of memory chips and a logic chip stacked in a third direction, utilizing twisted connections between bit lines to reduce parasitic capacitance and coupling noise, allowing for closer bit line spacing and increased integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DRAM architecture with bit lines arranged in conventional manner is used, then manufacturing and operation are simpler, but parasitic capacitance between bit lines increases adversely affecting memory performance
Solution Approach 1:
The patent applies three-dimensional stacking architecture where memory chips are stacked in a third direction perpendicular to the bit line arrangement plane. This dimensional transition separates bit lines from adjacent bit lines in the vertical dimension, reducing parasitic capacitance coupling while maintaining planar integration density.
Solution Approach 2:
The patent divides the memory system into multiple stacked memory chip layers, with each layer containing storage structures and bit lines. This segmentation isolates bit lines in different physical layers, reducing mutual capacitance interference and improving signal integrity for sense amplifier operations.
2Quantity of substance
If bit lines are spaced closer to increase integration density, then storage density improves, but parasitic capacitance and coupling noise increase reducing sense margin
Solution Approach 1:
By stacking memory chips in the third dimension, the patent achieves higher storage density without reducing planar bit line spacing. The vertical separation between stacked layers provides electrical isolation that maintains sense margin while increasing overall capacity through multi-layer integration.
Solution Approach 2:
The patent introduces through-silicon vias and interconnect structures as intermediary elements between stacked memory chip layers. These intermediaries provide controlled impedance paths and electrical isolation, enabling close bit line spacing in each layer while maintaining signal integrity through the stacking architecture.
3Ease of operation
If multiple sense amplifiers are connected to bit lines in conventional DRAM, then data read operations can be performed, but large parasitic capacitance between bit lines degrades amplification accuracy
Solution Approach 1:
The three-dimensional stacked architecture physically separates bit lines connected to the same sense amplifier across different vertical layers. This spatial separation reduces capacitive coupling between bit lines during voltage difference amplification, improving measurement precision while maintaining ease of data read operations.
Solution Approach 2:
The patent employs through-silicon via structures as disposable interconnect elements that provide localized electrical pathways between stacked layers. These via structures minimize parasitic inductance and resistance while providing sufficient isolation for accurate sense amplifier operation.
Data Source
AI summary
Provided are a memory, including multiple layers of memory chips and a logic chip stacked in a third direction. Each of the memory chips includes multiple storage structures arranged in a first direction and a second direction. The ith bit line in a first storage structure is connected to the ith bit line in a fourth storage structure. The ith bit line in a third storage structure is connected to the ith bit line in a second storage structure. The first storage structure is adjacent to the third storage structure in the third direction. The fourth storage structure and the third storage structure are located in the same one of the memory chips. The second storage structure is adjacent to the fourth storage structure in the third direction. The second storage structure and the first storage structure are located in the same one of the memory chips.