Cell-on-Periphery Memory Core Layout for Compact DRAM Circuits
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Solution Overview
Problem
Conventional DRAM devices face challenges in reducing size due to limitations in circuit arrangement and implementation difficulty, especially with the use of vertical channel transistors, which restricts the miniaturization and integration efficiency.
Innovation Solution
A memory core circuit with a cell on periphery (CoP) structure, where the core control circuit is efficiently arranged under the memory cell array, dividing sub peripheral circuits into edge and central regions, optimizing the placement of bitline sense amplifiers and wordline drivers to enhance design margin and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional DRAM device structure is used with open bitline structure, then two bitlines are spread on both sides of the bitline sense amplifier, but the size reduction of the memory device is limited due to circuits for driving the memory cell array
Solution Approach 1:
The patent transitions from a conventional planar arrangement where peripheral circuits are located at the edges to a Cell-On-Periphery (CoP) structure where peripheral circuits are positioned underneath the memory cell array in the vertical dimension. This dimensional change allows bitline sense amplifiers to be located directly beneath bitlines and wordline drivers beneath wordlines, significantly reducing the overall device footprint while maintaining all necessary driving circuits
Solution Approach 2:
The patent implements nesting by placing peripheral circuits (bitline sense amplifiers and wordline drivers) underneath the memory cell array, effectively nesting the control circuits within the vertical space of the memory structure. This allows the peripheral circuits to share the same horizontal footprint as the memory cells above them, reducing the total device area
2Volume of moving object
If vertical channel transistor (VCT) is used to reduce size, then implementation difficulty increases and design margin decreases
Solution Approach 1:
The patent divides the peripheral circuit region into distinct segments: bitline sense amplifier regions positioned under specific bitlines and wordline driver regions positioned under specific wordlines. This segmentation allows each component to be independently designed, manufactured, and tested, reducing overall implementation difficulty while maintaining compact size
Solution Approach 2:
The patent applies local quality by optimizing the placement of different peripheral circuits in specific locations underneath the memory cell array. Bitline sense amplifiers are positioned where they can efficiently sense bitline voltages, while wordline drivers are positioned to optimally drive wordlines, enhancing both manufacturability and performance
3Reliability
If core control circuit is efficiently arranged under memory cell array, then design margin is enhanced and operation characteristics are improved, but circuit arrangement complexity increases
Solution Approach 1:
The CoP structure serves multiple functions simultaneously: it reduces device area, provides efficient electrical connections between peripheral circuits and memory cells, enables independent optimization of sense amplifiers and wordline drivers, and facilitates heat dissipation. This multi-functionality justifies the increased arrangement complexity by delivering comprehensive performance benefits
Data Source
AI summary
A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit including sub peripheral circuits respectively disposed under the sub cell arrays. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. The wordlines extend in a row direction and are arranged in a column direction. The bitlines extend in the column direction and are arranged in the row direction. Each sub peripheral circuit is divided into first and second column edge regions and a central region. The central region is between the first column edge region and the second column edge region. A sense amplifier region including a plurality of bitline sense amplifiers are in at least one of the first column edge region and the second column edge region. A wordline driver region including a plurality of sub wordline drivers is disposed in the central region.